ented applications. The device is byte controlled. A buff-
tion.
hold unused or floating data inputs at a valid logic level.
鈩?/div>
series
resistors in the outputs. This design reduces line noise in
applications such as memory address drivers, clock drivers
and bus transceivers/transmitters.
The 74ALVCH162374 is designed for low voltage
(1.65V to 3.6V) V
CC
applications with output compatibility
up to 3.6V.
The 74ALVCH162374 is fabricated with an advanced
CMOS technology to achieve high speed operation while
maintaining low CMOS power dissipation.
Features
s
1.65V to 3.6V V
CC
supply operation
s
3.6V tolerant control inputs and outputs
s
Bushold data inputs eliminates the need for external
pull-up/pull-down resistors
s
26
鈩?/div>
series resistors in outputs
s
t
PD
(CLK to O
n
)
4.6 ns max for 3.0V to 3.6V V
CC
5.4 ns max for 2.3V to 2.7V V
CC
9.6 ns max for 1.65V to 1.95V V
CC
s
Uses patented noise/EMI reduction circuitry
s
Latch-up conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Ordering Code:
Order Number
74ALVCH162374T
Package
Number
MTD48
Package Descriptions
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
CP
n
I
0
鈥揑
15
O
0
鈥揙
15
Description
Output Enable Input (Active LOW)
Clock Pulse Input
Bushold Inputs
Outputs
漏 2002 Fairchild Semiconductor Corporation
DS500628
www.fairchildsemi.com
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