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74ALVC162835T Datasheet

  • 74ALVC162835T

  • Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant I...

  • 7頁(yè)

  • FAIRCHILD

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74ALVC162835 Low Voltage 18-Bit Universal Bus Driver with 3.6V Tolerant Inputs/Outputs and 26鈩?Series
Resistors in Outputs
September 2001
Revised February 2002
74ALVC162835
Low Voltage 18-Bit Universal Bus Driver
with 3.6V Tolerant Inputs/Outputs
and 26
鈩?/div>
Series Resistors in Outputs
General Description
The ALVC162835 low voltage 18-bit universal bus driver
combines D-type latches and D-type flip-flops to allow data
flow in transparent, latched and clocked modes.
Data flow is controlled by output-enable (OE), latch-enable
(LE), and clock (CLK) inputs. The device operates in
Transparent Mode when LE is held HIGH. The device
operates in clocked mode when LE is LOW and CLK is tog-
gled. Data transfers from the Inputs (I
n
) to Outputs (O
n
) on
a Positive Edge Transition of the Clock. When OE is LOW,
the output data is enabled. When OE is HIGH the output
port is in a high impedance state.
The ALVC162835 is designed with 26
鈩?/div>
series resistors in
the outputs. This design reduces noise in applications such
as memory address drivers, clock drivers, and bus trans-
ceivers/transmitters.
The 74ALVC162835 is designed for low voltage (1.65V to
3.6V) V
CC
applications with I/O capability up to 3.6V.
The 74ALVC162835 is fabricated with an advanced CMOS
technology to achieve high speed operation while maintain-
ing low CMOS power dissipation.
Features
s
Compatible with PC100 DIMM module specifications
s
1.65V to 3.6V V
CC
specifications provided
s
3.6V tolerant inputs and outputs
s
26
鈩?/div>
series resistors in outputs
s
t
PD
(CLK to O
n
)
5.4 ns max for 3.0V to 3.6V V
CC
6.3 ns max for 2.3V to 2.7V V
CC
9.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion/withdrawal (Note 1)
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high impedance state during power up or power
down, OE should be tied to V
CC
through a pulldown resistor; the minimum
value of the resistor is determined by the current sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC162835T
Package
Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2002 Fairchild Semiconductor Corporation
DS500646
www.fairchildsemi.com

74ALVC162835T 產(chǎn)品屬性

  • Fairchild Semiconductor

  • CMOS

  • ALVC

  • 18

  • LVTTL

  • LVTTL

  • 3-State

  • - 12 mA

  • 12 mA

  • 6.1 ns

  • 3.6 V

  • 1.65 V

  • + 85 C

  • TSSOP W

  • Rail

  • Universal Bus Driver

  • - 40 C

  • SMD/SMT

  • 1

  • Non-Inverting

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