outputs.
ing low CMOS power dissipation.
鈩?/div>
series resistors in outputs
s
t
PD
3.9 ns max for 3.0V to 3.6V V
CC
4.6 ns max for 2.3V to 2.7V V
CC
8.2 ns max for 1.65V to 1.95V V
CC
s
Power-off high impedance inputs and outputs
s
Supports live insertion and withdrawal (Note 1)
s
Uses patented noise/EMI reduction circuitry
s
Latchup conforms to JEDEC JED78
s
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC162827T
Package Number
MTD56
Package Description
56-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix 鈥淴鈥?to the ordering code.
Logic Symbol
Pin Descriptions
Pin Names
OE
n
I
0
鈥揑
19
O
0
鈥揙
19
Description
Output Enable Input (Active LOW)
Inputs
Outputs
漏 2001 Fairchild Semiconductor Corporation
DS500698
www.fairchildsemi.com