resistance in the A Port outputs. This design reduces line
clock drivers, and bus transceivers/transmitters.
ing low CMOS power dissipation.
鈩?/div>
series resistors in A Port outputs
I
t
PD
3.9 ns max for 3.0V to 3.6V V
CC
4.8 ns max for 2.3V to 2.7V V
CC
8.6 ns max for 1.65V to 1.95V V
CC
I
Power-down high impedance inputs and outputs
I
Supports live insertion/withdrawal (Note 1)
I
Uses patented noise/EMI reduction circuitry
I
Latchup conforms to JEDEC JED78
I
ESD performance:
Human body model
>
2000V
Machine model
>
200V
Note 1:
To ensure the high-impedance state during power up or power
down, OE should be tied to V
CC
through a pull-up resistor; the minimum
value of the resistor is determined by the current-sourcing capability of the
driver.
Ordering Code:
Order Number
74ALVC162245T
Package Number
MTD48
Package Description
48-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 6.1mm Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter 鈥淴鈥?to the ordering code.
漏 2001 Fairchild Semiconductor Corporation
DS500679
www.fairchildsemi.com