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74AHC2G126 Datasheet

  • 74AHC2G126

  • Dual buffer/line driver; 3-state

  • 100.78KB

  • 20頁

  • PHILIPS

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74AHC2G126; 74AHCT2G126
Dual buffer/line driver; 3-state
Rev. 02 鈥?21 September 2004
Product data sheet
1. General description
The 74AHC2G126; AHCT2G126 is a high-speed Si-gate CMOS device.
The 74AHC2G126; AHCT2G126 provides a dual non-inverting buffer/line driver with
3-state output. The 3-state output is controlled by the output enable input (OE). A LOW at
pin nOE causes the output to assume a high-impedance OFF-state.
2. Features
s
Symmetrical output impedance
s
High noise immunity
s
ESD protection:
x
HBM EIA/JESD22-A114-B exceeds 2000 V
x
MM EIA/JESD22-A115-A exceeds 200 V
x
CDM EIA/JESD22-C101 exceeds 1000 V.
s
Low power dissipation
s
Balanced propagation delays
s
Multiple package options
s
Speci鏗乪d from
鈭?0 擄C
to +85
擄C
and from
鈭?0 擄C
to +125
擄C.
3. Quick reference data
Table 1:
Quick reference data
GND = 0 V; T
amb
= 25
擄
C; t
r
= t
f
鈮?/div>
3.0 ns.
Symbol
t
PHL
, t
PLH
C
I
C
PD
Parameter
propagation delay
nA to nY
input capacitance
power dissipation
capacitance
C
L
= 50 pF; f
i
= 1 MHz
[1] [2]
Conditions
C
L
= 15 pF; V
CC
= 5 V
Min
-
-
-
Typ
3.4
1.5
10
Max
5.5
10
-
Unit
ns
pF
pF
Type 74AHC2G126

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