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74AHC16373DGGRE4 Datasheet

  • 74AHC16373DGGRE4

  • 16-BIT TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

  • 13頁

  • TI

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SN54AHC16373, SN74AHC16373
16-BIT TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCLS329G 鈥?MARCH 1996 鈥?REVISED JANUARY 2000
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
鈩?/div>
Family
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) Process
Operating Range 2-V to 5.5-V V
CC
Distributed V
CC
and GND Pins Minimize
High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
Latch-Up Performance Exceeds 250 mA Per
JESD 17
ESD Protection Exceeds 2000 V Per
MIL-STD-883, Method 3015; Exceeds 200 V
Using Machine Model (C = 200 pF, R = 0)
Package Options Include Plastic Shrink
Small-Outline (DL), Thin Shrink
Small-Outline (DGG), and Thin Very
Small-Outline (DGV) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54AHC16373 . . . WD PACKAGE
SN74AHC16373 . . . DGG, DGV, OR DL PACKAGE
(TOP VIEW)
description
The 鈥橝HC16373 devices are 16-bit transparent
D-type latches with 3-state outputs designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
1OE
1Q1
1Q2
GND
1Q3
1Q4
V
CC
1Q5
1Q6
GND
1Q7
1Q8
2Q1
2Q2
GND
2Q3
2Q4
V
CC
2Q5
2Q6
GND
2Q7
2Q8
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1LE
1D1
1D2
GND
1D3
1D4
V
CC
1D5
1D6
GND
1D7
1D8
2D1
2D2
GND
2D3
2D4
V
CC
2D5
2D6
GND
2D7
2D8
2LE
These devices can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high,
the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels at the
D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect internal operations of the latch. Old data can be retained or new data can be entered while
the outputs are in the high-impedance state.
The SN54AHC16373 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C.
The SN74AHC16373 is characterized for operation from 鈥?0擄C to 85擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
2000, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74AHC16373DGGRE4 產(chǎn)品屬性

  • Texas Instruments

  • 閉鎖

  • 2

  • D-Type Transparent Latch

  • AHC

  • Non-Inverting

  • 16

  • - 8 mA

  • 32 mA

  • 14 ns at 3.3 V, 9.2 ns at 5 V

  • 5.5 V

  • 2 V

  • + 85 C

  • - 40 C

  • TSSOP-48

  • Reel

  • SMD/SMT

  • 16

  • 2000

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