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74ACTQ273 Datasheet

  • 74ACTQ273

  • Quiet Series Octal D-Type Flip-Flop

  • 109.55KB

  • 9頁(yè)

  • FAIRCHILD

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74ACTQ273 Quiet Series Octal D-Type Flip-Flop
August 1989
Revised November 1999
74ACTQ273
Quiet Series Octal D-Type Flip-Flop
General Description
The ACTQ273 has eight edge-triggered D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) and Master Reset (MR) input load and
reset (clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D-
type input, one setup time before the LOW-to-HIGH clock
transition, is transferred to the corresponding flip-flop鈥檚 Q
output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
The ACTQ utilizes Fairchild Quiet Series錚?technology to
guarantee quiet output switching and improved dynamic
threshold performance. FACT Quiet Series錚?features
GTO錚?output control and undershoot corrector in addition
to a split ground bus for superior performance.
Features
s
I
CC
reduced by 50%
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Improved latch-up immunity
s
Buffered common clock and asynchronous master reset
s
Outputs source/sink 24 mA
s
4 kV minimum ESD immunity
Ordering Code:
Order Number
74ACTQ273SC
74ACTQ273SJ
74ACTQ273MTC
74ACTQ273PC
Package Number
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit, JEDEC MS-013, 0.300鈥?Wide Body
20-Lead Small Outline Package, EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package, JEDEC MS-001, 0.300鈥?Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
鈥揇
7
MR
CP
Q
0
鈥換
7
Description
Data Inputs
Master Reset
Clock Pulse Input
Data Outputs
FACT錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 1999 Fairchild Semiconductor Corporation
DS010585
www.fairchildsemi.com

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