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74ACT280TTR Datasheet

  • 74ACT280TTR

  • Parity Generator/Checker

  • 9頁(yè)

  • ETC

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74ACT280
9 BIT PARITY GENERATOR/CHECKER
s
s
s
s
s
s
s
s
s
HIGH SPEED: t
PD
= 7ns (TYP.) at V
CC
= 5V
LOW POWER DISSIPATION:
I
CC
= 4碌A(chǔ)(MAX.) at T
A
=25擄C
COMPATIBLE WITH TTL OUTPUTS
V
IH
= 2V (MIN.), V
IL
= 0.8V (MAX.)
50鈩?TRANSMISSION LINE DRIVING
CAPABILITY
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 24mA (MIN)
BALANCED PROPAGATION DELAYS:
t
PLH
鈮?/div>
t
PHL
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 4.5V to 5.5V
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES 280
IMPROVED LATCH-UP IMMUNITY
DIP
SOP
TSSOP
ORDER CODES
PACKAGE
DIP
SOP
TSSOP
TUBE
74ACT280B
74ACT280M
T&R
74ACT280MTR
74ACT280TTR
DESCRIPTION
The 74ACT280 is an advanced high-speed CMOS
9 BIT PARITY GENERATOR CHECKER
fabricated with sub-micron silicon gate and
double-layer metal wiring C
2
MOS tecnology.
It is composed of nine data inputs (A to I) and odd/
even parity outputs (危ODD and
危EVEN).
The nine
data inputs control the output conditions. When
the number of high level input is odd,
危ODD
output is kept high and
危EVEN
output low.
PIN CONNECTION AND IEC LOGIC SYMBOLS
Conservely, when the output is even,
危EVEN
output is kept high and
危ODD
low.
The IC generates either odd or even parity making
it flexible application. The word-length capability is
easly expanded by cascading.
The device is designed to interface directly High
Speed CMOS systems with TTL, NMOS and
CMOS output voltage levels.
All inputs and outputs are equipped with
protection circuits against static discharge, giving
them 2KV ESD immunity and transient excess
voltage.
April 2001
1/9

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