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74ACT16827DLR Datasheet

  • 74ACT16827DLR

  • 20-BIT BUFFERS/DRIVERS WITH 3-STATE OUTPUTS

  • 8頁

  • TI

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54ACT16827, 74ACT16827
20-BIT BUFFERS/DRIVERS
WITH 3-STATE OUTPUTS
SCAS163A 鈥?JUNE 1990 鈥?REVISED APRIL 1996
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
鈩?/div>
Family
Inputs Are TTL-Voltage Compatible
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes
PCB Layout
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) Packages Using
25-mil Center-to-Center Pin Spacings and
380-mil Fine-Pitch Ceramic Flat (WD)
Packages Using 25-mil Center-to-Center
Pin Spacings
54ACT16827 . . . WD PACKAGE
74ACT16827 . . . DL PACKAGE
(TOP VIEW)
description
The 鈥橝CT16827 are noninverting 20-bit buffers
composed of two 10-bit sections with separate
output-enable signals. For either 10-bit buffer
section, the two output-enable (1OE1 and 1OE2
or 2OE1 and 2OE2) inputs must both be low for
the corresponding Y outputs to be active. If either
output-enable input is high, the outputs of that
10-bit buffer section are in the high-impedance
state.
The 74ACT16827 is packaged in TI鈥檚 shrink
small-outline package, which provides twice the
I/O pin count and functionality of standard
small-outline packages in the same printed-
circuit-board area.
1OE1
1Y1
1Y2
GND
1Y3
1Y4
V
CC
1Y5
1Y6
1Y7
GND
1Y8
1Y9
1Y10
2Y1
2Y2
2Y3
GND
2Y4
2Y5
2Y6
V
CC
2Y7
2Y8
GND
2Y9
2Y10
2OE1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OE2
1A1
1A2
GND
1A3
A14
V
CC
1A5
1A6
1A7
GND
1A8
1A9
1A10
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2A9
2A10
2OE2
The 54ACT16827 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C. The
74ACT16827 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
(each 8-bit section)
INPUTS
OE1
L
L
H
X
OE2
L
L
X
H
A
L
H
X
X
OUTPUT
Y
L
H
Z
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1996, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74ACT16827DLR 產(chǎn)品屬性

  • 1,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74ACT

  • 緩沖器/線路驅(qū)動(dòng)器，非反相

  • 2

  • 10

  • 24mA，24mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-BSSOP（0.295"，7.50mm 寬）

  • 56-SSOP

  • 帶卷 (TR)

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