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Local Bus-Latch Capability
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125擄C
Package Options Include Plastic Small-
Outline Packages and Standard Plastic
300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
t
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
GAB
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
GBA
description
The 74ACT11623 is designed for asynchronous two-way communication between data buses. The control
function implementation allows for maximum flexibility in timing.
The device allows data transmission from the A bus to the B bus or from the B bus to the A bus depending upon
the logic levels at the enable inputs (GBA and GAB). The enable inputs can be used to disable the device so
that the buses are effectively isolated.
The dual-enable configuration gives these devices the capability to store data by simultaneous enabling of GBA
and GAB. Each output reinforces its input in this transceiver configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets of bus lines are at high impedance, both sets of bus lines (16
in all) will remain at their last states. The 8-bit codes appearing on the two sets of buses will be identical for the
74ACT11623.
The 74ACT11623 is characterized for operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
ENABLE INPUTS
GBA
GAB
L
L
H
H
H
L
L
H
OPERATION
B data to A bus
A data to B bus
Isolation
B data to A bus,
A data to B bus
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
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DALLAS, TEXAS 75265
2鈥?
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