鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages and Standard Plastic (N) 300-mil
DIPs
DB, DW, N, OR PW PACKAGE
(TOP VIEW)
1Y
2Y
3Y
GND
GND
GND
GND
4Y
5Y
6Y
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
1A
2A
3A
NC
V
CC
V
CC
NC
4A
5A
6A
NC 鈥?No internal connection
description
This device contains six independent inverters. It performs the Boolean function Y = A.
The 74ACT11004 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
(each inverter)
INPUT
A
H
L
OUTPUT
Y
L
H
logic symbol
鈥?/div>
1A
2A
3A
4A
5A
6A
20
19
18
13
12
11
1
1
2
3
8
9
10
1Y
2Y
3Y
4Y
5Y
6Y
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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