dynamic threshold performance. FACT Quiet Series fea-
錚?/div>
addition to a split ground bus or superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Combines the 245 and the 280 functions in one package
s
300 mil 24-pin slim dual-in-line package
s
Outputs source/sink 24 mA
s
ACTQ has TTL-compatible inputs
Ordering Code:
Order Number
74ACQ657SPC
74ACTQ657SC
74ACTQ657SPC
Package Number
N24C
M24B
N24C
Package Description
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code
Logic Symbols
IEEE/IEC
Connection Diagram
Pin Descriptions
Pin Names
A
0
鈥揂
7
B
0
鈥揃
7
T/R
OE
PARITY
ODD/EVEN
ERROR
Description
Data Inputs/3-STATE Outputs
Data Inputs/3-STATE Outputs
Transmit/Receive Input
Enable Input
Parity Input/3-STATE Output
ODD/EVEN Parity Input
Error 3-STATE Output
FACT錚? Quiet Series錚? FACT Quiet Series錚? and GTO錚?are trademarks of Fairchild Semiconductor Corporation.
漏 2000 Fairchild Semiconductor Corporation
DS010636
www.fairchildsemi.com