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74ACQ464ASPC Datasheet

  • 74ACQ464ASPC

  • Quiet Series⑩ Octal Transceiver/Register with 3-STATE Outpu...

  • 99.62KB

  • 10頁

  • FAIRCHILD

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74ACQ646 鈥?74ACTQ646 Quiet Series錚?Octal Transceiver/Register with 3-STATE Outputs
January 1990
Revised September 2000
74ACQ646 鈥?74ACTQ646
Quiet Series
錚?/div>
Octal Transceiver/Register
with 3-STATE Outputs
General Description
The ACQ/ACTQ646 consist of registered bus transceiver
circuits, with outputs, D-type flip-flops, and control circuitry
providing multiplexed transmission of data directly from the
input bus or from the internal storage registers. Data on the
A or B bus will be loaded into the respective registers on
the LOW-to-HIGH transition of the appropriate clock pin
(CPAB or CPBA). The four fundamental handling functions
available are illustrated in Figure 1, Figure 2, Figure 3 and
Figure 4.
The ACQ/ACTQ utilizes Fairchild Quiet Series
錚?/div>
technol-
ogy to guarantee quiet output switching and improved
dynamic threshold performance. FACT Quiet Series
錚?/div>
fea-
tures GTO
錚?/div>
output control and undershoot corrector in
addition to a split ground bus for superior performance.
Features
s
Guaranteed simultaneous switching noise level and
dynamic threshold performance
s
Guaranteed pin-to-pin skew AC performance
s
Independent registers for A and B busses
s
Multiplexed real-time and stored data transfers
s
300 mil slim dual-in-line package
s
Outputs source/sink 24 mA
s
Faster prop delays than the standard AC/ACT646
Ordering Code:
Order Number
74ACQ646SC
74ACQ464ASPC
74ACTQ646SC
74ACTQ464ASPC
Package Number
M24B
N24C
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
A
0
鈥揂
7
B
0
鈥揃
7
CPAB, CPBA
SAB, SBA
G
DIR
Descriptions
Data Register A Inputs
Data Register A Outputs
Data Register B Inputs
Data Register B Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Input
Direction Control Input
FACT錚? Quiet Series錚? FACT Quiet Series錚?and GTO錚?are trademarks of Fairchild Semiconductor Corporation
漏 2000 Fairchild Semiconductor Corporation
DS010635
www.fairchildsemi.com

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