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74AC648SPC Datasheet

  • 74AC648SPC

  • Single 8-Bit Inverting Bus Transceiver

  • 75.80KB

  • 7頁(yè)

  • FAIRCHILD

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74AC648 Octal Transceiver/Register with 3-STATE Outputs
November 1988
Revised August 2000
74AC648
Octal Transceiver/Register with 3-STATE Outputs
General Description
The AC648 consists of registered bus transceiver circuits,
with outputs, D-type flip-flops and control circuitry providing
multiplexed transmission of data directly from the input bus
or from the internal storage registers. Data on the A or B
bus will be loaded into the respective registers on the
LOW-to-HIGH transition of the appropriate clock pin (CPAB
or CPBA). The four fundamental data handling functions
available are illustrated in Figure 1, Figure 2, Figure 3, and
Figure 4.
Features
s
Independent registers for A and B buses
s
Multiplexed real-time and stored data transfers
s
3-STATE outputs
s
300 mil slim dual-in-line package
s
Outputs source/sink 24 mA
s
Inverted data to output
Ordering Code:
Order Number
74AC648SC
74AC648SPC
Package Number
M24B
N24C
Package Description
24-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
24-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
A
0
鈥揂
7
B
0
鈥?B
7
CPAB, CPBA
SAB, SBA
DIR, G
Description
Data Register A Inputs,
Data Register A 3-STATE Outputs
Data Register B Inputs,
Data Register B 3-STATE Outputs
Clock Pulse Inputs
Transmit/Receive Inputs
Output Enable Inputs
FACT錚?is a trademark of Fairchild Semiconductor Corporation.
漏 2000 Fairchild Semiconductor Corporation
DS010133
www.fairchildsemi.com

74AC648SPC 產(chǎn)品屬性

  • 375

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74AC

  • 收發(fā)器，非反相

  • 1

  • 8

  • 24mA，24mA

  • 2 V ~ 6 V

  • -40°C ~ 85°C

  • 通孔

  • 24-DIP（0.300"，7.62mm）

  • 24-PDIP

  • 管件

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