74AC377 鈥?74ACT377 Octal D-Type Flip-Flop with Clock Enable
November 1988
Revised March 2005
74AC377 鈥?74ACT377
Octal D-Type Flip-Flop with Clock Enable
General Description
The AC/ACT377 has eight edge-triggered, D-type flip-flops
with individual D inputs and Q outputs. The common buff-
ered Clock (CP) input loads all flip-flops simultaneously,
when the Clock Enable (CE) is LOW.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
The CE input must be stable only one setup time prior to
the LOW-to-HIGH clock transition for predictable operation.
Features
s
I
CC
reduced by 50%
s
Ideal for addressable register applications
s
Clock enable for address and data synchronization
applications
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Outputs source/sink 24 mA
s
See 273 for master reset version
s
See 373 for transparent latch version
s
See 374 for 3-STATE version
s
ACT377 has TTL-compatible inputs
Ordering Code:
Order Number
74AC377SC
74AC377SJ
74AC377MTC
74AC377MTCX_NL
(Note 1)
74AC377PC
74ACT377SC
74ACT377SJ
74ACT377MTC
74ACT377PC
Package
Number
M20B
M20D
MTC20
MTC20
N20A
M20B
M20D
MTC20
N20A
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Pb-Free 20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm
Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide
Pb-Free 20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Pb-Free package per JEDEC J-STD-020B.
Note 1:
鈥淿NL鈥?indicates Pb-Free package (per JEDEC J-STD-020B). Device available in Tape and Reel only.
Connection Diagram
Pin Descriptions
Pin Names
D
0
鈥揇
7
CE
Q
0
鈥換
7
CP
Description
Data Inputs
Clock Enable (Active LOW)
Data Outputs
Clock Pulse Input
FACT
樓
is a trademark of Fairchild Semiconductor Corporation.
漏 2005 Fairchild Semiconductor Corporation
DS009961
www.fairchildsemi.com
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