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74AC11640 Datasheet

  • 74AC11640

  • OCTAL BUS TRANSCEIVER WITH 3?STATE OUTPUTS

  • 6頁(yè)

  • TI

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74AC11640
OCTAL BUS TRANSCEIVER
WITH 3鈥揝TATE OUTPUTS
SCAS052A 鈥?JULY 1987 鈥?REVISED APRIL 1993
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Bidirectional Bus Transceivers in
High-Density 24-Pin Packages
Flow-Through Architecture Optimizes PCB
Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline Packages and Standard
Plastic 300-mil DIPs
DW OR NT PACKAGE
(TOP VIEW)
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIR
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
OE
description
These octal bus transceivers are designed for asynchronous communication between data buses. These
devices transmit data from the A bus to the B bus or from the B bus to the A bus depending upon the level at
the direction-control (DIR) input. The output-enable (OE) input can be used to disable the device so that the
buses are effectively isolated.
The 74AC11640 is characterized for operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
INPUTS
OE
L
L
H
DIR
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1993, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1

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