鈥?/div>
Eight D-Type Flip-Flops in a Single Package
3-State Bus Driving Inverting Outputs
Full Parallel Access for Loading
Inputs Are TTL-Voltage Compatible
Flow-Through Architecture to Optimize
PCB Layout
Center-Pin V
CC
and GND Configurations to
Minimize High-Speed Switching Noise
EPIC
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity
at 125擄C
Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic 300-mil
DIPs
54AC11534 . . . JT PACKAGE
74AC11534 . . . DW OR NT PACKAGE
(TOP VIEW)
t
1Q
2Q
3Q
4Q
GND
GND
GND
GND
5Q
6Q
7Q
8Q
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
OC
1D
2D
3D
4D
V
CC
V
CC
5D
6D
7D
8D
CLK
54AC11534 . . . FK PACKAGE
(TOP VIEW)
description
These eight flip-flops feature 3-state outputs
designed for implementing buffer registers, I/O
ports, bidirectional bus drivers, and working
registers.
The eight flip-flops of the
鈥睞C11534
are edge-
triggered, D-type flip-flops. On the positive
transition of the clock, the Q outputs are set to the
complement of the logic levels at the D inputs. The
鈥睞C11534
is functionally equivalent to the
鈥睞C11374
except for having inverted outputs.
An output-control input (OC) is used to place the
eight outputs in either a normal logic state (high or
low logic levels) or a high-impedance state. In the
high-impedance state, the outputs neither load
nor drive the bus lines significantly.
The
high-impedance third state and increased drive
provide the capability to drive the bus lines in a
bus-organized system without need for interface
or pull-up components. The output control (OC)
does not affect the internal operation of the
flip-flops. Old data can be retained or new data
can be entered while the outputs are in the
high-impedance state.
The 54AC11534 is characterized for operation
over the full military temperature range of 鈥?55擄C
to 125擄C. The 74AC11534 is characterized for
operation from 鈥?40擄C to 85擄C.
3D
4D
VCC
NC
VCC
5D
6D
2D
1D
OC
NC
1Q
2Q
3Q
5
6
7
8
9
10
4
3 2 1 28 27 26
25
24
23
22
21
20
11
19
12 13 14 15 16 17 18
7D
8D
CLK
NC
8Q
7Q
6Q
NC 鈥?No internal connection
OC
L
L
L
H
4Q
GND
GND
NC
GND
GND
5Q
FUNCTION TABLE
(each filp-flop)
INPUTS
CLK
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L
X
D
H
L
X
X
OUTPUT
Q
L
H
Q0
Z
Copyright
漏
1993, Texas Instruments Incorporated
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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