74AC11245
OCTAL BUS TRANSCEIVER
WITH 3-STATE OUTPUTS
SCAS010B 鈥?JULY 1987 鈥?REVISED APRIL 1996
D
D
D
D
D
D
3-State Outputs Drive Bus Lines Directly
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
t
(Enhanced-Performance Implanted
CMOS) 1-
m
m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), and Thin Shrink Small-Outline (PW)
Packages, and Standard Plastic 300-mil
DIPs (NT)
DB, DW, NT, OR PW PACKAGE
(TOP VIEW)
A1
A2
A3
A4
GND
GND
GND
GND
A5
A6
A7
A8
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
DIR
B1
B2
B3
B4
V
CC
V
CC
B5
B6
B7
B8
OE
description
This octal bus transceiver is designed for asynchronous two-way communication between data buses. The
control-function implementation minimizes external timing requirements.
The device allows noninverted data transmission from the A bus to the B bus or from the B bus to the A bus,
depending on the logic level at the direction-control (DIR) input. The output-enable (OE) input can be used to
disable the device so that the buses are effectively isolated.
The 74AC11245 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
OUTPUT
ENABLE
OE
L
L
H
DIRECTION
CONTROL
DIR
L
H
X
OPERATION
B data to A bus
A data to B bus
Isolation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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