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74AC11138D Datasheet

  • 74AC11138D

  • 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER

  • 8頁

  • TI

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74AC11138
3-LINE TO 8-LINE DECODER/DEMULTIPLEXER
SCAS042B 鈥?MAY 1988 鈥?REVISED APRIL 1996
D
D
D
D
D
D
Designed Specifically for High-Speed
Memory Decoders and Data Transmission
Systems
Incorporates Three Enable Inputs to
Simplify Cascading and/or Data Reception
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity at
125擄C
Package Options Include Plastic
Small-Outline (D) and Thin Shrink
Small-Outline (PW) Packages, and
Standard Plastic 300-mil DIPs (N)
D, N, OR PW PACKAGE
(TOP VIEW)
Y1
Y2
Y3
GND
Y4
Y5
Y6
Y7
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Y0
A
B
C
V
CC
G1
G2A
G2B
description
The 74AC11138 circuit is designed to be used in high-performance memory-decoding or data-routing
applications requiring very short propagation delay times. In high-performance memory systems, this decoder
can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing
a fast enable circuit, the delay times of this decoder and the enable time of the memory are usually less than
the typical access time of the memory. This means that the effective system delay introduced by the decoder
is negligible.
The conditions at the binary-select (A, B, C) inputs and the three enable (G1, G2A, G2B) inputs select one of
eight output lines. Two active-low and one active-high enable inputs reduce the need for external gates or
inverters when expanding. A 24-line decoder can be implemented without external inverters and a 32-line
decoder requires only one inverter. An enable input can be used as a data input for demultiplexing applications.
The 74AC11138 is characterized for operation from 鈥?0擄C to 85擄C.
FUNCTION TABLE
ENABLE INPUTS
G1
X
X
L
H
H
H
H
H
H
H
H
G2A
H
X
X
L
L
L
L
L
L
L
L
G2B
X
H
X
L
L
L
L
L
L
L
L
SELECT INPUTS
C
X
X
X
L
L
L
L
H
H
H
H
B
X
X
X
L
L
H
H
L
L
H
H
A
X
X
X
L
H
L
H
L
H
L
H
Y0
H
H
H
L
H
H
H
H
H
H
H
Y1
H
H
H
H
L
H
H
H
H
H
H
Y2
H
H
H
H
H
L
H
H
H
H
H
OUTPUTS
Y3
H
H
H
H
H
H
L
H
H
H
H
Y4
H
H
H
H
H
H
H
L
H
H
H
Y5
H
H
H
H
H
H
H
H
L
H
H
Y6
H
H
H
H
H
H
H
H
H
L
H
Y7
H
H
H
H
H
H
H
H
H
H
L
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1996, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
POST OFFICE BOX 1443 HOUSTON, TEXAS 77251鈥?443
鈥?/div>
鈥?/div>
1

74AC11138D 產(chǎn)品屬性

  • 40

  • 集成電路 (IC)

  • 邏輯 - 信號(hào)開關(guān)，多路復(fù)用器，解碼器

  • 74AC

  • 解碼器/多路分解器

  • 1 x 3:8

  • 1

  • 24mA，24mA

  • 單電源

  • 3 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 16-SOIC（0.154"，3.90mm 寬）

  • 16-SOIC N

  • 管件

  • 296-32792-574AC11138D-ND

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