鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity
at 125擄C
ESD Protection Exceeds 2000 V,
MIL STD-883C Method 3015
Package Options Include Plastic Small-
Outline Packages, Ceramic Chip Carriers,
and Standard Plastic and Ceramic
300-mil DIPs
54AC11112 . . . J PACKAGE
74AC11112 . . . D OR N PACKAGE
(TOP VIEW)
1PRE
1Q
1Q
GND
2Q
2Q
2PRE
2J
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
1J
1K
1CLK
1CLR
V
CC
2CLR
2CLK
2K
54AC11112 . . . FK PACKAGE
(TOP VIEW)
description
These devices contain two independent J-K
negative-edge-triggered flip-flops. A low level at
the preset (PRE) or clear (CLR) inputs sets or
resets the outputs regardless of the levels of the
other inputs. When preset and clear are inactive
(high), data at the J and K inputs meeting the setup
time requirements are transferred to the outputs
on the negative-going edge of the clock pulse.
Clock triggering occurs at a voltage level and is not
directly related to the fall time of the clock pulse.
Following the hold time interval, data at the J and
K inputs may be changed without affecting the
levels at the outputs. These versatile flip-flops can
perform as toggle flip-flops by tying J and K high.
1K
1J
NC
1PRE
1Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1CLK
1CLR
NC
V CC
2CLR
2CLK
2K
NC
2J
2PRE
NC 鈥?No internal connection
FUNCTION TABLE
(each gate)
INPUTS
PRE
L
H
H
H
H
H
H
CLR
H
L
L
H
H
H
H
H
CLK
X
X
X
鈫?/div>
鈫?/div>
鈫?/div>
鈫?/div>
H
J
X
X
X
L
H
L
H
X
K
X
X
X
L
L
H
H
X
OUTPUTS
Q
H
L
H
{
QO
H
L
Toggle
QO
QO
Q
L
H
H
{
QO
L
H
鈥?This configuration is nonstable; that is, it will not persist
when either PRE or CLR returns to its inactive (high) level.
The 54AC11112 is characterized for operation over the full military temperature range of 鈥?55擄C to 125擄C. The
74AC11112 is characterized for operation from 鈥?40擄C to 85擄C.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
Copyright
漏
1993, Texas Instruments Incorporated
2鈥?
74AC11112相關(guān)型號PDF文件下載
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描述
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QUAD 2-INPUT AND GATE
1
2
3
4
5
6
7
