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74AC11030 Datasheet

  • 74AC11030

  • 8-INPUT POSITIVE-NAND GATES

  • 5頁

  • TI

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54AC11030, 74AC11030
8-INPUT POSITIVE-NAND GATES
SCAS001A 鈥?JUNE 1987 鈥?REVISED APRIL 1993
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Flow-Through Architecture Optimizes
PCB Layout
Center-Pin V
CC
and GND Configurations
Minimize High-Speed Switching Noise
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
500-mA Typical Latch-Up Immunity
at 125擄C
Package Options Include Plastic
Small-Outline Packages, Ceramic Chip
Carriers, and Standard Plastic and Ceramic
300-mil DIPs
54AC11030 . . . J PACKAGE
74AC11030 . . . D OR N PACKAGE
(TOP VIEW)
C
B
A
GND
Y
NC
NC
1
2
3
4
5
6
7
14
13
12
11
10
9
8
D
E
F
V
CC
NC
G
H
description
These devices contain a single 8-input NAND gate
and perform the following Boolean functions in
positive logic:
Y = A
鈥?/div>
B
鈥?/div>
C
鈥?/div>
D
鈥?/div>
E
鈥?/div>
F
鈥?/div>
G
鈥?/div>
H or
Y=A+B+C+D+E+F+G+H
The 54AC11030 is characterized for operation
over the full military temperature range of 鈥?55擄C
to 125擄C. The 74AC11030 is characterized for
operation from 鈥?40擄C to 85擄C.
FUNCTION TABLE
INPUTS
A THRU H
All inputs H
One or more inputs L
OUTPUT
Y
L
H
54AC11030 . . . FK PACKAGE
(TOP VIEW)
D
NC
C
NC
B
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
E
F
NC
V
CC
NC
G
NC
H
NC
NC
NC 鈥?No internal connection
logic symbol
鈥?/div>
A
B
C
D
E
F
G
H
3
2
1
14
13
12
9
8
5
Y
&
logic diagram (positive logic)
A
B
C
D
E
F
G
H
3
2
1
14
13
12
9
8
5
Y
鈥?This symbol is in accordance with ANSI/IEEE Std 91-1984
and IEC Publication 617-12.
Pin numbers shown are for the D, J, and N packages.
EPIC is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
A
GND
NC
Y
NC
Copyright
漏
1993, Texas Instruments Incorporated
2鈥?

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