鈥?/div>
Power-up Reset
DESCRIPTION
The 74ABT821 high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT821 Bus interface Register is designed to eliminate the
extra packages required to buffer existing registers and provide
and 200 V per Machine Model
required with MOS microprocessors
extra data width for wider data/address paths of buses carrying
parity.
The 74ABT821 is a buffered 10-bit wide version of the
74ABT374/74ABT534 functions.
The 74ABT821 is a 10-bit, edge triggered register coupled to ten
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition is transferred to
the corresponding flip-flop鈥檚 Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors.
The active Low Output Enable (OE) controls all ten 3-State buffers
independent of the register operation. When OE is Low, the data in
the register appears at the outputs. When OE is High, the outputs
are in high impedance 鈥漮ff鈥?state, which means they will neither drive
nor load the bus.
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25擄C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
4.6
4
7
500
UNIT
ns
pF
pF
nA
ORDERING INFORMATION
PACKAGES
24-Pin Plastic DIP
24-Pin plastic SO
24-Pin Plastic SSOP Type II
24-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
OUTSIDE NORTH AMERICA
74ABT821 N
74ABT821 D
74ABT821 DB
74ABT821 PW
NORTH AMERICA
74ABT821 N
74ABT821 D
74ABT821 DB
74ABT821PW DH
DWG NUMBER
SOT222-1
SOT137-1
SOT340-1
SOT355-1
PIN CONFIGURATION
OE
D0
D1
D2
D3
D4
D5
D6
D7
1
2
3
4
5
6
TOP VIEW
7
8
9
18
17
16
15
14
13
Q5
Q6
Q7
Q8
Q9
CP
24
23
22
21
20
19
V
CC
Q0
Q1
Q2
Q3
Q4
PIN DESCRIPTION
PIN NUMBER
1
2, 3, 4, 5, 6,
7, 8, 9, 10, 11
23, 22, 21, 20, 19,
18, 17, 16, 15, 14
13
10
20
SYMBOL
OE
D0-D9
Q0-Q9
CP
GND
V
CC
FUNCTION
Output enable input
(active-Low)
Data inputs
Data outputs
Clock pulse input (active
rising edge)
Ground (0V)
Positive supply voltage
D8 10
D9 11
GND 12
SA00223
1995 Sep 06
1
853-1616 15703
1
2
3
4
5
6
