鈥?/div>
ESD protection exceeds 2000 V per MIL STD 883 Method 3015
and 200 V per Machine Model
DESCRIPTION
The 74ABT374A high-performance BiCMOS device combines low
static and dynamic power dissipation with high speed and high
output drive.
The 74ABT374A is an 8-bit, edge triggered register coupled to eight
3-State output buffers. The two sections of the device are controlled
independently by the clock (CP) and Output Enable (OE) control
gates.
The register is fully edge triggered. The state of each D input, one
set-up time before the Low-to-High clock transition, is transferred to
the corresponding flip-flop鈥檚 Q output.
The 3-State output buffers are designed to drive heavily loaded
3-State buses, MOS memories, or MOS microprocessors. The
active-Low Output Enable (OE) controls all eight 3-State buffers
independent of the clock operation.
When OE is Low, the stored data appears at the outputs. When OE
is High, the outputs are in the High-impedance 鈥淥FF鈥?state, which
means they will neither drive nor load the bus.
鈥?/div>
Power-up 3-State
鈥?/div>
Power-up reset
鈥?/div>
Live insertion/extraction permitted
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
CP to Qn
Input capacitance
Output capacitance
Total supply current
CONDITIONS
T
amb
= 25擄C; GND = 0V
C
L
= 50pF; V
CC
= 5V
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or V
CC
Outputs disabled; V
CC
=5.5V
TYPICAL
3.4
3.8
4
7
110
UNIT
ns
pF
pF
碌A(chǔ)
ORDERING INFORMATION
PACKAGES
20-Pin Plastic DIP
20-Pin plastic SO
20-Pin Plastic SSOP Type II
20-Pin Plastic TSSOP Type I
TEMPERATURE RANGE
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
鈥?0擄C to +85擄C
OUTSIDE NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374A PW
NORTH AMERICA
74ABT374A N
74ABT374A D
74ABT374A DB
74ABT374APW DH
DWG NUMBER
SOT146-1
SOT163-1
SOT339-1
SOT360-1
PIN CONFIGURATION
PIN DESCRIPTION
PIN
NUMBER
SYMBOL
OE
D0-D7
FUNCTION
Output enable input (active-Low)
Data inputs
OE
Q0
D0
D1
Q1
Q2
D2
D3
Q3
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
V
CC
Q7
D7
D6
Q6
Q5
D5
D4
Q4
CP
1
3, 4, 7, 8,
13, 14, 17,
18
2, 5, 6, 9,
12, 15, 16,
19
11
10
20
Q0-Q7
CP
GND
V
CC
Data outputs
Clock pulse input (active rising edge)
Ground (0V)
Positive supply voltage
GND 10
SA00110
1995 Sep 06
1
853-1448 15704
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2
3
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