音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

74ABT273CMSA Datasheet

  • 74ABT273CMSA

  • Octal D-Type Flip-Flop

  • 101.51KB

  • 9頁(yè)

  • FAIRCHILD

掃碼查看芯片數(shù)據(jù)手冊(cè)

上傳產(chǎn)品規(guī)格書

PDF預(yù)覽

74ABT273 Octal D-Type Flip-Flop
January 1993
Revised November 1999
74ABT273
Octal D-Type Flip-Flop
General Description
The ABT273 has eight edge-triggered D-type flip-flops with
individual D inputs and Q outputs. The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously.
The register is fully edge-triggered. The state of each D
input, one setup time before the LOW-to-HIGH clock transi-
tion, is transferred to the corresponding flip-flop鈥檚 Q output.
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input. The
device is useful for applications where the true output only
is required and the Clock and Master Reset are common to
all storage elements.
Features
s
Eight edge-triggered D-type flip-flops
s
Buffered common clock
s
Buffered, asynchronous Master Reset
s
See ABT377 for clock enable version
s
See ABT373 for transparent latch version
s
See ABT374 for 3-STATE version
s
Output sink capability of 64 mA, source capability of
32 mA
s
Guaranteed latchup protection
s
High impedance glitch free bus loading during entire
power up and power down cycle
s
Non-destructive hot insertion capability
s
Disable time less than enable time to avoid bus conten-
tion
Ordering Code:
Order Number
74ABT273CSC
74ABT273CSJ
74ABT273CMSA
74ABT273CMTC
Package Number
M20B
M20D
MSA20
MTC20
Package Description
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300鈥?Wide Body
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Shrink Small Outline Package (SSOP), EIAJ TYPE II, 5.3mm Wide
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
Device also available in Tape and Reel. Specify by appending suffix letter 鈥淴鈥?to the ordering code.
Connection Diagram
Pin Descriptions
Pin Names
D
0
鈥揇
7
MR
CP
Q
0
鈥換
7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
Description
漏 1999 Fairchild Semiconductor Corporation
DS011549
www.fairchildsemi.com

74ABT273CMSA 產(chǎn)品屬性

  • 66

  • 集成電路 (IC)

  • 邏輯 - 觸發(fā)器

  • 74ABT

  • 主復(fù)位

  • D 型總線

  • 非反相

  • 1

  • 8

  • 200MHz

  • 6ns

  • 正邊沿

  • 32mA，64mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 20-SSOP（0.209"，5.30mm 寬）

  • 管件

74ABT273CMSA相關(guān)型號(hào)PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號(hào)推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務(wù)：
賣家服務(wù)：
技術(shù)客服：

0571-85317607

網(wǎng)站技術(shù)支持

13606545031

客服在線時(shí)間周一至周五
9:00-17:30

關(guān)注官方微信號(hào)，
第一時(shí)間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫(kù)提出的寶貴意見，您的參與是維庫(kù)提升服務(wù)的動(dòng)力！意見一經(jīng)采納，將有感恩紅包奉上哦！