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74ABT16952DGGRE4 Datasheet

  • 74ABT16952DGGRE4

  • 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS

  • 10頁(yè)

  • TI

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SN54ABT16952, SN74ABT16952
16-BIT REGISTERED TRANSCEIVERS
WITH 3-STATE OUTPUTS
SCBS082C 鈥?FEBRUARY 1991 鈥?REVISED JANUARY 1997
D
D
D
D
D
D
D
D
Members of the Texas Instruments
Widebus
鈩?/div>
Family
State-of-the-Art
EPIC-
螜螜
B
鈩?/div>
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25擄C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes PCB
Layout
High-Drive Outputs (鈥?2-mA I
OH
, 64-mA I
OL
)
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54ABT16952 . . . WD PACKAGE
SN74ABT16952 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
The 鈥橝BT16952 are 16-bit registered transceivers
that contain two sets of D-type flip-flops for
temporary storage of data flowing in either
direction. The 鈥橝BT16952 can be used as two 8-bit
transceivers or one 16-bit transceiver. Data on the
A or B bus is stored in the registers on the
low-to-high transition of the clock (CLKAB or
CLKBA) input provided that the clock-enable
(CLKENAB or CLKENBA) input is low. Taking the
output-enable (OEAB or OEBA) input low
accesses the data on either port.
1OEAB
1CLKAB
1CLKENAB
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2CLKENAB
2CLKAB
2OEAB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEBA
1CLKBA
1CLKENBA
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2CLKENBA
2CLKBA
2OEBA
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT16952 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C.
The SN74ABT16952 is characterized for operation from 鈥?0擄C to 85擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus and EPIC-螜螜B are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1997, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
1

74ABT16952DGGRE4 產(chǎn)品屬性

  • 2,000

  • 集成電路 (IC)

  • 邏輯 - 緩沖器，驅(qū)動(dòng)器，接收器，收發(fā)器

  • 74ABT

  • 寄存收發(fā)器，非反相

  • 2

  • 8

  • 32mA，64mA

  • 4.5 V ~ 5.5 V

  • -40°C ~ 85°C

  • 表面貼裝

  • 56-TFSOP（0.240"，6.10mm 寬）

  • 56-TSSOP

  • 帶卷 (TR)

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