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BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25擄C
Distributed V
CC
and GND Pin Configuration
Minimizes High-Speed Switching Noise
Flow-Through Architecture Optimizes
PCB Layout
High-Drive Outputs (鈥?2-mA I
OH
, 64-mA I
OL
)
Parity-Error Flag With Parity
Generator/Checker
Latch for Storage of the Parity-Error Flag
Package Options Include Plastic 300-mil
Shrink Small-Outline (DL) and Thin Shrink
Small-Outline (DGG) Packages and 380-mil
Fine-Pitch Ceramic Flat (WD) Package
Using 25-mil Center-to-Center Spacings
SN54ABT16853 . . . WD PACKAGE
SN74ABT16853 . . . DGG OR DL PACKAGE
(TOP VIEW)
description
The 鈥橝BT16853 dual 8-bit to 9-bit parity
transceivers are designed for communication
between data buses. When data is transmitted
from the A bus to the B bus, a parity bit is
generated. When data is transmitted from the
B bus to the A bus, with its corresponding parity
bit, the open-collector parity-error (ERR) output
indicates whether or not an error in the B data has
occurred. The output-enable (OEA and OEB)
inputs can be used to disable the device so that
the buses are effectively isolated. The 鈥橝BT16853
provide true data at the outputs.
1OEB
1LE
1ERR
GND
1A1
1A2
V
CC
1A3
1A4
1A5
GND
1A6
1A7
1A8
2A1
2A2
2A3
GND
2A4
2A5
2A6
V
CC
2A7
2A8
GND
2ERR
2LE
2OEB
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
1OEA
1CLR
1PARITY
GND
1B1
1B2
V
CC
1B3
1B4
1B5
GND
1B6
1B7
1B8
2B1
2B2
2B3
GND
2B4
2B5
2B6
V
CC
2B7
2B8
GND
2PARITY
2CLR
2OEA
A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports
with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the
latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from
the A bus to the B bus, and inverted parity is generated. Inverted parity is a forced error condition that gives the
designer more system diagnostic capability.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-螜螜B and Widebus are trademarks of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1997, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
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