DM74174 Hex/Quad D-Type Flip-Flop with Clear
September 1986
Revised February 2000
DM74174
Hex/Quad D-Type Flip-Flop with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry
to implement D-type flip-flop logic. All have a direct clear
input.
Information at the D inputs meeting the setup and hold time
requirements is transferred to the Q outputs on the posi-
tive-going edge of the clock pulse. Clock triggering occurs
at a particular voltage level and is not directly related to the
transition time of the positive-going pulse. When the clock
input is at either the HIGH or LOW level, the D input signal
has no effect at the output.
Features
s
Contains six flip-flops with single-rail outputs
s
Buffered clock and direct clear inputs
s
Individual data input to each flip-flop
s
Applications include:
Buffer/storage registers
Shift registers
Pattern generators
s
Typical clock frequency 40 MHz
s
Typical power dissipation per flip-flop 38 mW
Ordering Code:
Order Number
DM74174
Package Number
N16E
Package Description
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
(Each Flip-Flop)
Inputs
Clear
L
H
H
H
Clock
X
鈫?/div>
鈫?/div>
L
D
X
H
L
X
Outputs
Q
L
H
L
Q
0
H
=
HIGH Level (steady state)
L
=
LOW Level (steady state)
X
=
Don鈥檛 Care
鈫?=
Transition from LOW-to-HIGH level
Q
0
=
The level of Q before the indicated steady-state input conditions were
established.
漏 2000 Fairchild Semiconductor Corporation
DS006557
www.fairchildsemi.com
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