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74112 Datasheet

  • 74112

  • DUAL J-K FLIP FLOP WITH PRESET AND CLEAR

  • 11頁

  • STMICROELECTRONICS   STMICROELECTRONICS

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M54HC112
M74HC112
DUAL J-K FLIP FLOP WITH PRESET AND CLEAR
.
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 67 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 2
碌A(chǔ)
AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
|I
OH
| = I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE
WITH 54/74LS112
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC112F1R
M74HC112M1R
M74HC112B1R
M74HC112C1R
DESCRIPTION
The M54/74HC112 is a high speed CMOS DUAL J-K
FLIP-FLOP WITH PRESET AND CLEAR fabricated in
silicon gate C
2
MOS technology. It has the same high
speed performance of LSTTL combined with true
CMOS
low
power
consumption.
The
M54HC112/M74HC112 dual JK flip-flop features indi-
vidual J,K, clock, and asynchronous set and clearinputs
for each flip-flop. When the clock goes high, the inputs
are enabled and data will be accepted. The logic level
of the J and K inputs may be allowed to change when
the clock pulse is high and the bistable will function as
shown in the truth table. Input data is transferred to the
input on the negative going edge of the clock pulse. All
inputs are equipped withprotection circuits against static
discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
October 1992
1/11

74112 產(chǎn)品屬性

  • 10

  • 工具

  • 螺釘和螺母驅(qū)動器 - 刀片和位

  • -

  • 十字槽鉆頭

  • #2

  • 1.97"（50mm）

  • -

  • 0.25 磅（113.4g）

  • 38025-ND - TOOL MAGNETC BIT HOLDR 1/4" 6BIT38800-ND - TOOL BIT HOLDER T-HANDLE 1/4"38015-ND - TOOL BIT HOLDER MAGNETIC 1/4"

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