.
.
.
.
.
.
.
.
錚OH錚?/div>
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS107
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC107F1R
M74HC107M1R
M74HC107B1R
M74HC107C1R
DESCRIPTION
The M54/74HC107 is a high speed CMOS DUAL J-
K FLIP FLOP fabricated in silicon gate C
2
MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. These flip-flop are edge sensitive to the
clock input and change state on the negative going
transition of the clock pulse. Each one has inde-
pendent J, K, CLOCK, and CLEAR input and Q and
Q outputs. CLEAR is independent of the clock and
accomplished by a logic low on the input. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
October 1992
1/11