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74107 Datasheet

  • 74107

  • DUAL J-K FLIP FLOP WITH CLEAR

  • 11頁(yè)

  • STMICROELECTRONICS   STMICROELECTRONICS

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M54HC107
M74HC107
DUAL J-K FLIP FLOP WITH CLEAR
.
.
.
.
.
.
.
.
HIGH SPEED
f
MAX
= 75 MHz (TYP.) AT V
CC
= 5 V
LOW POWER DISSIPATION
I
CC
= 2
碌A(chǔ)
(MAX.) AT T
A
= 25
擄C
HIGH NOISE IMMUNITY
V
NIH
= V
NIL
= 28 % V
CC
(MIN.)
OUTPUT DRIVE CAPABILITY
10 LSTTL LOADS
SYMMETRICAL OUTPUT IMPEDANCE
錚OH錚?/div>
= I
OL
= 4 mA (MIN.)
BALANCED PROPAGATION DELAYS
t
PLH
= t
PHL
WIDE OPERATING VOLTAGE RANGE
V
CC
(OPR) = 2 V TO 6 V
PIN AND FUNCTION COMPATIBLE WITH
54/74LS107
B1R
(Plastic Package)
F1R
(Ceramic Package)
M1R
(Micro Package)
C1R
(Chip Carrier)
ORDER CODES :
M54HC107F1R
M74HC107M1R
M74HC107B1R
M74HC107C1R
DESCRIPTION
The M54/74HC107 is a high speed CMOS DUAL J-
K FLIP FLOP fabricated in silicon gate C
2
MOS tech-
nology. It has the same high speed performance of
LSTTL combined with true CMOS low power con-
sumption. These flip-flop are edge sensitive to the
clock input and change state on the negative going
transition of the clock pulse. Each one has inde-
pendent J, K, CLOCK, and CLEAR input and Q and
Q outputs. CLEAR is independent of the clock and
accomplished by a logic low on the input. All inputs
are equipped with protection circuits against static
discharge and transient excess voltage.
INPUT AND OUTPUT EQUIVALENT CIRCUIT
PIN CONNECTIONS
(top view)
NC =
No Internal
Connection
October 1992
1/11

74107 產(chǎn)品屬性

  • 0現(xiàn)貨

  • 1 : ￥50.75000散裝

  • -

  • 散裝

  • 停產(chǎn)

  • 刀頭，電動(dòng)

  • 十字

  • #0

  • 1/4"

  • 3.50"（88.9mm）

  • 防撞擊

  • 1

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