DM7403 Quad 2-Input NAND Gates with Open-Collector Outputs
August 1986
Revised February 2000
DM7403
Quad 2-Input NAND Gates with Open-Collector Outputs
General Description
This device contains four independent gates each of which
performs the logic NAND function. The open-collector out-
puts require external pull-up resistors for proper logical
operation.
Pull-Up Resistor Equations
Where:
N
1
(I
OH
)
=
total maximum output high current
for all outputs tied to pull-up resistor
N
2
(I
IH
)
=
total maximum input high current for
all inputs tied to pull-up resistor
N
3
(I
IL
)
=
total maximum input low current for
all inputs tied to pull-up resistor
Ordering Code:
Order Number
DM7403N
Package Number
N14A
Package Description
14-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Connection Diagram
Function Table
Y
=
AB
Inputs
A
L
L
H
H
H
=
HIGH Logic Level
L
=
LOW Logic Level
Output
B
L
H
L
H
Y
H
H
H
L
漏 2000 Fairchild Semiconductor Corporation
DS006493
www.fairchildsemi.com