音影先锋亚洲天堂网|电影世界尽头的爱完整版播放|国产 熟女 91|高清无码免费观看欧美日韩|韩国一区二区三区黄色录像|美女亚洲加勒比在线|亚洲综合网 开心五月|7x成人在线入口|成人网站免费日韩毛片区|国产黄片?一级?二级?三级

71V433S12PF Datasheet

  • 71V433S12PF

  • 32K x 32 3.3V Synchronous SRAM Flow-Through Outputs

  • 19頁

  • IDT

掃碼查看芯片數(shù)據(jù)手冊

上傳產品規(guī)格書

PDF預覽

32K x 32
3.3V Synchronous SRAM
Flow-Through Outputs
Features
32K x 32 memory configuration
Supports high performance system speed:
Commercial and Industrial:
鈥?11 11ns Clock-to-Data Access (50MHz)
鈥?12 12ns Clock-to-Data Access (50MHz)
LBO
input selects interleaved or linear burst mode
Self-timed write cycle with global write control (GW), byte
write enable (BWE), and byte writes (BWx)
Power down controlled by ZZ input
Single 3.3V power supply (+10/-5%)
Packaged in a JEDEC Standard 100-pin rectangular plastic
thin quad flatpack (TQFP).
IDT71V433
x
x
x
x
x
x
x
Description
The IDT71V433 is a 3.3V high-speed 1,048,576-bit SRAM orga-
nized as 32K x 32 with full support of various processor interfaces
including the Pentium鈩?and PowerPC鈩? The flow-through burst archi-
tecture provides cost-effective 2-1-1-1 performance for processors up to
50 MHz.
The IDT71V433 SRAM contains write, data-input, address and
control registers. There are no registers in the data output path (flow-
through architecture). Internal logic allows the SRAM to generate a
self-timed write based upon a decision which can be left until the
extreme end of the write cycle.
The burst mode feature offers the highest level of performance to
the system designer, as the IDT71V433 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from
the array after a clock-to-data access time delay from the rising clock
edge of the same cycle. If burst mode operation is selected (ADV=LOW),
the subsequent three cycles of output data will be available to the
user on the next three rising clock edges. The order of these three
addresses will be defined by the internal burst counter and the
LBO
input pin.
The IDT71V433 SRAM utilizes IDT's high-performance 3.3V
CMOS process, and is packaged in a JEDEC Standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP).
Pin Description
A
0
鈥揂
14
CE
CS
0
,
CS
1
OE
GW
BWE
BW
1
鈥揃W
4
CLK
ADV
ADSC
ADSP
LBO
ZZ
I/O
0
鈥揑/O
31
V
DD
, V
DDQ
V
SS
, V
SSQ
Address Inputs
Chip Enable
Chips Selects
Output Enable
Global Write Enable
Byte Write Enable
Individual Byte Write Selects
Clock Input
Burst Address Advance
Address Status (Cache Controller)
Address Status (Processor)
Linear / Interleaved Burst Order
Sleep Mode
Data Input/Output
Co re and I/O Power Supply (3.3V)
Array Ground, I/O Ground
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
Power
Power
Synchronous
Synchronous
Synchronous
Asynchronous
Synchronous
Synchronous
Synchronous
N/A
Synchronous
Synchronous
Synchronous
DC
Asynchronous
Synchronous
N/A
N/A
3729 tbl 01
Pentium is a trademark of Intel Corp.
PowerPC is a trademark of International Business Machines, Inc.
AUGUST 2001
1
DSC-3729/04
漏2000 Integrated Device Technology, Inc.

71V433S12PF相關型號PDF文件下載

您可能感興趣的PDF文件資料

熱門IC型號推薦

掃碼下載APP，
一鍵連接廣大的電子世界。

在線人工客服

買家服務：
賣家服務：
技術客服：

0571-85317607

網站技術支持

13606545031

客服在線時間周一至周五
9:00-17:30

關注官方微信號，
第一時間獲取資訊。

建議反饋
返回頂部

建議反饋

聯(lián)系人：

聯(lián)系方式：

按住滑塊，拖拽到最右邊
>>
感謝您向阿庫提出的寶貴意見，您的參與是維庫提升服務的動力！意見一經采納，將有感恩紅包奉上哦！