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PRELIMINARY

HIGH-SPEED 32K x 9

SYNCHRONOUS PIPELINED

DUAL-PORT STATIC RAM

.eatures

x

x

IDT709179L

x

x

x

x

True Dual-Ported memory cells which allow simultaneous

access of the same memory location

High-speed clock to data access

鈥?Commercial: 7.5/9/12ns (max.)

鈥?Industrial: 9ns (max)

Low-power operation

鈥?IDT709179L

Active: 1.2W (typ.)

Standby: 2.5mW (typ.)

Flow-Through or Pipelined output mode on either Port via

the

FT/PIPE

pins

Counter enable and reset features

Dual chip enables allow for depth expansion without

x

x

x

x

additional logic

Full synchronous operation on both ports

鈥?4ns setup to clock and 0ns hold on all control, data, and

address inputs

鈥?Data input, address, and control registers

鈥?Fast 7.5ns clock to data out in the Pipelined output mode

鈥?Self-timed write allows fast cycle time

鈥?12ns cycle time, 83MHz operation in Pipelined output mode

TTL- compatible, single 5V (鹵10%) power supply

Industrial temperature range (鈥?0擄C to +85擄C) is

available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP) package

.unctional Block Diagram

R/W

L

OE

L

CE

0L

CE

1L

R/W

R

OE

R

CE

0R

CE

1R

1

0

0/1

1

0

0/1

FT/PIPE

L

0/1

1

0

0

1

0/1

FT/PIPE

R

I/O

0L

- I/O

8L

I/O

0R

- I/O

8R

I/O

Control

I/O

Control

A

14L

A

0L

CLK

L

ADS

L

CNTEN

L

CNTRST

L

Counter/

Address

Reg.

MEMORY

ARRAY

Counter/

Address

Reg.

A

14R

A

0R

CLK

R

ADS

R

CNTEN

R

CNTRST

R

5644 drw 01

AUGUST 2001

1

漏2001 Integrated Device Technology, Inc.

DSC-5644/1

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