CDP68HC68W1
March 1998
CMOS Serial Digital Pulse Width Modulator
Description
The CDP68HC68W1 modulates a clock input to supply a
variable frequency and duty-cycle output signal. Three 8-bit
registers (pulse width, frequency and control) are accessed
serially after power is applied to initialize device operation.
The value in the pulse width register selects the high
duration of the output period. The frequency register byte
divides the clock input frequency and determines the overall
output clock period. The input clock can be further divided by
two or a low power mode may be selected by the lower two
bits in the control register. A comparator circuit allows
threshold control by setting the output low if the input at the
V
T
pin rises above 0.75V. The CDP68HC68W1 is supplied in
an 8 lead PDIP package (E suf鏗亁).
Features
鈥?Programmable Frequency and Duty Cycle Output
鈥?Serial Bus Input; Compatible with Motorola/Intersil
SPI Bus, Simple Shift-Register Type Interface
鈥?8 Lead PDIP Package
鈥?Schmitt Trigger Clock Input
鈥?4V to 6V Operation, -40
o
C to 85
o
C Temperature Range
鈥?8MHz Clock Input Frequency
Pinout
CDP68HC68W1
(PDIP)
TOP VIEW
CLK
CS
V
T
V
SS
1
2
3
4
8
7
6
5
V
DD
PWM
SCK
DATA
Ordering Information
PART NUMBER
CDP68HC68W1E
TEMP. RANGE
(
o
C)
-40 to 85
PACKAGE
8 Ld PDIP
PKG.
NO.
E8.3
Block Diagram
CLK
INPUT CLK
MODULATOR
LOGIC
PWM
8 - STAGE RIPPLE
COUNTER
8 - STAGE RIPPLE
COUNTER
RESET
PULSE - WIDTH
DATA REGISTER
LOAD
FREQUENCY
DATA REGISTER
LOAD
DATA
8 - STAGE SHIFT
REGISTER
8 - STAGE SHIFT
REGISTER
CONTROL REGISTER
2 - STAGE SHIFT
LOAD
V
T
V
T
COMPARATOR
SCK
8
16
24
5 - STAGE 24 - STATE
COMPARATOR
CS
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
File Number
1919.3
1