ACS02MS
Data Sheet
November 1998
File Number
4540
Radiation Hardened Quad 2-Input NOR Gate
The Radiation Hardened ACS02MS is a Quad 2-Input NOR
Gate. For each gate, a HIGH level on either A or B input
results in a LOW level on the Y output. A LOW level on both
the A and B inputs results in a HIGH level on the Y output.
All inputs are buffered and the outputs are designed for
balanced propagation delay and transition times.
The ACS02MS is fabricated on a CMOS Silicon on
Sapphire (SOS) process, which provides an immunity to
Single Event Latch-up and the capability of highly reliable
performance in any radiation environment. These devices
offer significant power reduction and faster performance
when compared to ALSTTL types.
Speci鏗乧ations for Rad Hard QML devices are controlled
by the Defense Supply Center in Columbus (DSCC). The
SMD numbers listed below must be used when ordering.
Detailed Electrical Speci鏗乧ations for the ACS02MS are
contained in SMD 5962-98601. A 鈥渉ot-link鈥?is provided
on our homepage with instructions for downloading.
www.intersil.com/data/sm/index.asp
Features
鈥?QML Quali鏗乪d Per MIL-PRF-38535 Requirements
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Radiation Environment
- Latch-Up Free Under Any Conditions
- Total Dose. . . . . . . . . . . . . . . . . . . . . . . 3 x 10
5
RAD(Si)
- SEU Immunity . . . . . . . . . . . . . <1 x 10
-10
Errors/Bit/Day
- SEU LET Threshold . . . . . . . . . . . . >100MeV/(mg/cm
2
)
鈥?Input Logic Levels. . . . V
IL
= (0.3)(V
CC
), V
IH
= (0.7)(V
CC
)
鈥?Output Current . . . . . . . . . . . . . . . . . . . . . . . .
鹵8mA
(Min)
鈥?Quiescent Supply Current . . . . . . . . . . . . . . 100碌A(chǔ) (Max)
鈥?Propagation Delay . . . . . . . . . . . . . . . . . . . . . . 12ns (Max)
Applications
鈥?High Speed Control Circuits
鈥?Sensor Monitoring
鈥?Low Power Designs
Ordering Information
ORDERING NUMBER
5962F9860101VCC
ACS02D/SAMPLE-03
5962F9860101VXC
ACS02K/SAMPLE-03
5962F9860101V9A
INTERNAL MARKETING
NUMBER
ACS02DMSR-03
ACS02D/SAMPLE-03
ACS02KMSR-03
ACS02K/SAMPLE-03
ACS02HMSR-03
TEMP. RANGE (
o
C)
-55 to 125
25
-55 to 125
25
25
PACKAGE
14 Ld SBDIP
14 Ld SBDIP
14 Ld Flatpack
14 Ld Flatpack
Die
DESIGNATOR
CDIP2-T14
CDIP2-T14
CDFP4-F14
CDFP4-F14
N/A
Pinouts
ACS02MS
(SBDIP)
TOP VIEW
1Y 1
A1 2
B1 3
Y2 4
A2 5
B2 6
GND 7
14 V
CC
13 Y4
12 B4
11 A4
10 Y3
9 B3
8 A3
ACS02MS
(FLATPACK)
TOP VIEW
1Y
A1
B1
Y2
A2
B2
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
Y4
B4
A4
Y3
B3
A3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
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