ACTS161MS
January 1996
Radiation Hardened
4-Bit Synchronous Counter
Pinouts
16 PIN CERAMIC DUAL-IN-LINE
MIL-STD-1835, DESIGNATOR CDIP2-T16,
LEAD FINISH C
TOP VIEW
MR 1
CP 2
P0 3
P1 4
P2 5
P3 6
PE 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 TE
9 SPE
Features
鈥?Devices QML Quali鏗乪d in Accordance with MIL-PRF-38535
鈥?Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96716 and Intersil鈥檚 QM Plan
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity: <1 x 10
-10
Errors/Bit/Day
(Typ)
鈥?SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm
2
/mg
鈥?Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
鈥?Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
鈥?Input Current
鈮?/div>
1碌A(chǔ) at VOL, VOH
鈥?Fast Propagation Delay . . . . . . . . . . . . . . . . 25ns (Max), 16ns (Typ)
16 PIN CERAMIC FLATPACK
MIL-STD-1835, DESIGNATOR CDFP4-F16,
LEAD FINISH C
TOP VIEW
MR
CP
P0
P1
P2
P3
PE
GND
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VCC
TC
Q0
Q1
Q2
Q3
TE
SPE
Description
The Intersil ACTS161MS is a Radiation Hardened 4-Bit Binary Synchronous
Counter, featuring asynchronous reset and load ahead carry logic. The MR is
an active low master reset. SPE is an active low Synchronous Parallel Enable
which disables counting and allows data at the preset inputs (P0 - P3) to load
the counter. CP is the positive edge clock. TC is the terminal count or carry
output. Both TE and PE must be high for counting to occur, but are irrelevant
to loading. TE low will keep TC low.
The ACTS161MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS161MS is supplied in a 16 lead Ceramic Flatpack (K suf鏗亁) or
a Ceramic Dual-In-Line Package (D suf鏗亁).
Ordering Information
PART NUMBER
5962F9671601VEC
5962F9671601VXC
ACTS161D/Sample
ACTS161K/Sample
ACTS161HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
16 Lead SBDIP
16 Lead Ceramic Flatpack
16 Lead SBDIP
16 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright 漏 Intersil Corporation 1999
Spec Number
1
518893
File Number
4095
INTERSIL
1
2
3
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