ACS630MS
January 1996
Radiation Hardened EDAC
(Error Detection and Correction Circuit)
Pinouts
28 PIN CERAMIC DUAL-IN-LINE, MIL-STD-1835
DESIGNATOR CDIP2-T28, LEAD FINISH C
TOP VIEW
DEF 1
DB0 2
DB1 3
DB2 4
28 VCC
27 SEF
26 S1
25 S0
24 CB0
23 CB1
22 CB2
21 CB3
20 CB4
19 CB5
18 DB15
17 DB14
16 DB13
15 DB12
Features
鈥?Devices QML Quali鏗乪d in Accordance with MIL-PRF-38535
鈥?Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96711 and Intersil鈥?QM Plan
鈥?1.25 Micron Radiation Hardened SOS CMOS
鈥?Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
鈥?Single Event Upset (SEU) Immunity: <1 x 10
(Typ)
-10
Errors/Bit/Day
MEV-cm
2
/mg
鈥?SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100
DB3 5
DB4 6
DB5 7
DB6 8
DB7 9
DB8 10
DB9 11
DB10 12
DB11 13
GND 14
鈥?Dose Rate Upset . . . . . . . . . . . . . . . . >10
11
RAD (Si)/s, 20ns Pulse
鈥?Dose Rate Survivability . . . . . . . . . . . >10
12
RAD (Si)/s, 20ns Pulse
鈥?Latch-Up Free Under Any Conditions
鈥?Military Temperature Range . . . . . . . . . . . . . . . . . . -55
o
C to +125
o
C
鈥?Signi鏗乧ant Power Reduction Compared to ALSTTL Logic
鈥?DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
鈥?Input Logic Levels
- VIL = 30% of VCC Max
- VIH = 70% of VCC Min
鈥?Input Current
鈮?/div>
1碌A(chǔ) at VOL, VOH
鈥?Fast Propagation Delay . . . . . . . . . . . . . . . . 37ns (Max), 24ns (Typ)
Description
The Intersil ACS630MS is a Radiation Hardened 16-bit parallel error
detection and correction circuit. It uses a modi鏗乪d Hamming code to
generate a 6-bit check word from each 16-bit data word. The check word
is stored with the data word during a memory write cycle; during a
memory read cycle a 22-bit word is taken form memory and checked for
errors. Single bit errors in the data words are 鏗俛gged and corrected.
Single bit errors in check words are 鏗俛gged but not corrected. The
position of the incorrect bit is pinpointed, in both cases, by the 6-bit error
syndrome code which is output during the error correction cycle.
The ACS630MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic Family.
The ACS630MS is supplied in a 28 lead Ceramic Flatpack (K suf鏗亁) or a
28 Lead Ceramic Dual-In-Line Package (D suf鏗亁).
28 PIN CERAMIC FLATPACK, MIL-STD-1835
DESIGNATOR CDFP3-F28, LEAD FINISH C
TOP VIEW
DEF
DB0
DB1
DB2
DB3
DB4
DB5
DB6
DB7
DB8
DB9
DB10
DB11
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
SEF
S1
S0
CB0
CB1
CB2
CB3
CB4
CB5
DB15
DB14
DB13
DB12
Ordering Information
PART NUMBER
5962F9671101VXC
5962F9671101VYC
ACS630D/Sample
ACS630K/Sample
ACS630HMSR
TEMPERATURE RANGE
-55
o
C to +125
o
C
-55
o
C to +125
o
C
25
o
C
25
o
C
25
o
C
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
28 Lead SBDIP
28 Lead Ceramic Flatpack
28 Lead SBDIP
28 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207
|
Copyright
漏
Intersil Corporation 1999
Spec Number
File Number
1
518781
3199.1
INTERSIL
1
2
3
4
