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5962F8957701XX Datasheet

  • 5962F8957701XX

  • BCRTM

  • 61頁

  • ETC

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UT1553 BCRTM
F
EATURES
p
Comprehensive MIL-STD-1553 dual-redundant Bus
p
p
p
p
p
Controller (BC) and Remote Terminal (RT) and
Monitor (M) functions
MIL-STD-1773 compatible
Multiple message processing capability in BC
Time tagging and message logging in RT and M modes
Automatic polling and intermessage delay in
BC mode
Programmable interrupt scheme and internally
generated interrupt history list
p
Register-oriented architecture to enhance
p
p
p
p
p
p
programmability
DMA memory interface with 64K addressability
Internal self-test
Radiation-hardened option available for 84-lead
flatpack package only
Remote terminal operations in ASD/ENASD-certified
(SEAFAC)
Available in 84-pin pingrid array, 84-lead flatpack, 84-
lead leadless chip-carrier
Standard Microcircuit Drawing 5962-89577 available
- QML Q and V compliant
REGISTERS
CONTROL
HIGH-PRIORITY
STD PRIORITY LEVEL
STD PRIORITY PULSE
STATUS
CURRENT BC (or M) BLOCK/
RT DESCRIPTOR SPACE
POLLING COMPARE
CLOCK &
RESET
LOGIC
INTERRUPT
HANDLER
BC PROTOCOL
&
MESSAGE
HANDLER
BUILT-IN-TEST WORD
CURRENT COMMAND
INTERRUPT LOG
LIST POINTER
HIGH-PRIORITY
INTERRUPT ENABLE
16
HIGH-PRIORITY
INTERRUPT STATUS
STANDARD INTERRUPT
ENABLE
16
RT/MONITOR
PROTOCOL &
MESSAGE
HANDLER
BUILT-
IN-
TEST
16
RT ADDRESS
BUILT-IN-TEST
START COMMAND
RESET COMMAND
RT TIMER
RESET COMMAND
MONITOR ADDRESS
CONTROL
MONITOR ADDRESS
SELECT (0-15)
ADDRESS
MONITOR ADDRESS
SELECT (16-31)
16
16
DATA
12MHz
MASTER
RESET
1553
DATA
CHANNEL
A
1553
DATA
CHANNEL
B
DUAL
CHANNEL
ENCODER/
DECODER
MODULE
PARALLEL-
TO-SERIAL
CONVER-
SION
16
BUS
TRANSFER
LOGIC
SERIAL-TO-
PARALLEL
CONVER-
SION
TIMERON
TIMEOUT
ADDRESS
GENERATOR
16
DMA/CPU
CONTROL
16
DMA ARBITRATION
REGISTER CONTROL
DUAL-PORT MEMORY CONTROL
Figure 1. BCRTM Block Diagram
BCRTM-1

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