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5962-9866101VXA Datasheet

  • 5962-9866101VXA

  • FLOATING - POINT DIGITAL SIGNAL PROCESSOR

  • 63頁(yè)

  • TI

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SMJ320C6701
FLOATING POINT DIGITAL SIGNAL PROCESSOR
SGUS030B 鈥?APRIL 2000 鈥?REVISED MAY 2001
D
Highest Performance Floating-Point Digital
Signal Processor (DSP) SMJ320C6701
鈥?7-, 6-ns Instruction Cycle Time
鈥?140-, 167-MHz Clock Rate
鈥?Eight 32-Bit Instructions/Cycle
鈥?Up to 1 GFLOPS Performance
鈥?Pin-Compatible With 鈥機(jī)6201 Fixed-Point
DSP
SMJ: QML Processing to MIL-PRF-38535
SM: Standard Processing
Operating Temperature Ranges
鈥?Extended (W) 鈥?5擄C to 115擄C
鈥?Extended (S) 鈥?0擄C to 90擄C
VelociTI錚?Advanced Very Long Instruction
Word (VLIW) 鈥機(jī)67x CPU Core
鈥?Eight Highly Independent Functional
Units:
鈥?Four ALUs (Floating- and Fixed-Point)
鈥?Two ALUs (Fixed-Point)
鈥?Two Multipliers (Floating- and
Fixed-Point)
鈥?Load-Store Architecture With 32 32-Bit
General-Purpose Registers
鈥?Instruction Packing Reduces Code Size
鈥?All Instructions Conditional
Instruction Set Features
鈥?Hardware Support for IEEE
Single-Precision Instructions
鈥?Hardware Support for IEEE
Double-Precision Instructions
鈥?Byte-Addressable (8-, 16-, 32-Bit Data)
鈥?32-Bit Address Range
鈥?8-Bit Overflow Protection
鈥?Saturation
鈥?Bit-Field Extract, Set, Clear
鈥?Bit-Counting
鈥?Normalization
D
1M-Bit On-Chip SRAM
鈥?512K-Bit Internal Program/Cache
(16K 32-Bit Instructions)
鈥?512K-Bit Dual-Access Internal Data
(64K Bytes)
32-Bit External Memory Interface (EMIF)
鈥?Glueless Interface to Synchronous
Memories: SDRAM and SBSRAM
鈥?Glueless Interface to Asynchronous
Memories: SRAM and EPROM
Four-Channel Bootloading
Direct-Memory-Access (DMA) Controller
With an Auxiliary Channel
16-Bit Host-Port Interface (HPI)
鈥?Access to Entire Memory Map
Two Multichannel Buffered Serial Ports
(McBSPs)
鈥?Direct Interface to T1/E1, MVIP, SCSA
Framers
鈥?ST-Bus-Switching Compatible
鈥?Up to 256 Channels Each
鈥?AC97-Compatible
鈥?Serial-Peripheral-Interface (SPI)
Compatible (Motorola錚?
Two 32-Bit General-Purpose Timers
Flexible Phase-Locked-Loop (PLL) Clock
Generator
IEEE-1149.1 (JTAG
鈥?/div>
)
Boundary-Scan-Compatible
429-Pin Ceramic Ball Grid Array (CBGA)
Package (GLP Suffix)
0.18-碌m/5-Level Metal Process
鈥?CMOS Technology
3.3-V I/Os, 1.9-V Internal
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
VelociTI is a trademark of Texas Instruments Incorporated.
Motorola is a trademark of Motorola, Inc.
鈥?IEEE Standard 1149.1-1990 Standard-Test-Access Port and Boundary Scan Architecture.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
1

5962-9866101VXA 產(chǎn)品屬性

  • Texas Instruments

  • 數(shù)字信號(hào)處理器與控制器 (DSP, DSC)

  • 32 bit

  • 128 KB

  • 140 MHz

  • 1120 MIPs

  • 1.9 V

  • + 115 C

  • FC/CSP-429

  • SMD/SMT

  • TMS320

  • - 55 C

  • Tray

  • DSPs

  • Asynchronous SRAM, Synchronous SBSRAM, SDRAM

  • 1

  • TMS320

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