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5962-9686001QDA Datasheet

  • 5962-9686001QDA

  • DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AN...

  • 19頁

  • TI

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SN54AHC74, SN74AHC74
DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH CLEAR AND PRESET
SCLS255J 鈥?DECEMBER 1995 鈥?REVISED JULY 2003
D
D
Operating Range 2-V to 5.5-V V
CC
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
SN54AHC74 . . . FK PACKAGE
(TOP VIEW)
1CLR
1CLR
1D
1CLK
1PRE
1Q
1Q
GND
1
2
3
4
5
6
7
14
13
12
11
10
9
8
V
CC
2CLR
2D
2CLK
2PRE
2Q
2Q
1
14
13
2CLR
12
2D
11
2CLK
10
2PRE
9
2Q
1D
1CLK
1PRE
1Q
1Q
2
3
4
5
6
7
8
1D
1CLR
NC
V
CC
2CLR
1CLK
NC
1PRE
NC
1Q
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
V
CC
SN54AHC74 . . . J OR W PACKAGE
SN74AHC74 . . . D, DB, DGV, N, NS,
OR PW PACKAGE
(TOP VIEW)
SN74AHC74 . . . RGY PACKAGE
(TOP VIEW)
2D
NC
2CLK
NC
2PRE
GND
2Q
NC 鈥?No internal connection
description/ordering information
The 鈥橝HC74 dual positive-edge-triggered devices are D-type flip-flops.
A low level at the preset (PRE) or clear (CLR) inputs sets or resets the outputs, regardless of the levels of the
other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time
requirements is transferred to the outputs on the positive-going edge of the clock pulse. Clock triggering occurs
at a voltage level and is not directly related to the rise time of the clock pulse. Following the hold-time interval,
data at the D input can be changed without affecting the levels at the outputs.
ORDERING INFORMATION
TA
PACKAGE鈥?/div>
QFN 鈥?RGY
PDIP 鈥?N
SOIC 鈥?D
鈥?0擄C to 85擄C
SOP 鈥?NS
SSOP 鈥?DB
TSSOP 鈥?PW
TVSOP 鈥?DGV
CDIP 鈥?J
鈥?5擄C to 125擄C
CFP 鈥?W
LCCC 鈥?FK
Tape and reel
Tube
Tube
Tape and reel
Tape and reel
Tape and reel
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AHC74RGYR
SN74AHC74N
SN74AHC74D
SN74AHC74DR
SN74AHC74NSR
SN74AHC74DBR
SN74AHC74PW
SN74AHC74PWR
SN74AHC74DGVR
SNJ54AHC74J
SNJ54AHC74W
SNJ54AHC74FK
AHC74
HA74
HA74
HA74
SNJ54AHC74J
SNJ54AHC74W
SNJ54AHC74FK
TOP-SIDE
MARKING
HA74
SN74AHC74N
AHC74
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
1Q
GND
NC
2Q
2Q
1

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