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5962-9685401QSA Datasheet

  • 5962-9685401QSA

  • OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH 3-STATE OUTPUTS

  • 18頁

  • TI

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SN54AHC574, SN74AHC574
OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOPS
WITH 3-STATE OUTPUTS
SCLS244I 鈥?OCTOBER 1995 鈥?REVISED JULY 2003
D
D
D
Operating Range 2-V to 5.5-V V
CC
3-State Outputs Drive Bus Lines Directly
Latch-Up Performance Exceeds 250 mA Per
JESD 17
D
ESD Protection Exceeds JESD 22
鈥?2000-V Human-Body Model (A114-A)
鈥?200-V Machine Model (A115-A)
鈥?1000-V Charged-Device Model (C101)
SN54AHC574 . . . FK PACKAGE
(TOP VIEW)
2D
1D
OE
V
CC
SN54AHC574 . . . J OR W PACKAGE
SN74AHC574 . . . DB, DGV, DW, N, NS, OR PW PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
CLK
3D
4D
5D
6D
7D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
1Q
2Q
3Q
4Q
5Q
6Q
description/ordering information
The 鈥橝HC574 devices are octal edge-triggered D-type flip-flops that feature 3-state outputs designed
specifically for driving highly capacitive or relatively low-impedance loads. These devices are particularly
suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.
On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels of the data (D) inputs.
A buffered output-enable (OE) input places the eight outputs in either a normal logic state (high or low) or the
high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly.
The high-impedance state and the increased drive provide the capability to drive bus lines without interface or
pullup components.
ORDERING INFORMATION
TA
PDIP 鈥?N
SOIC 鈥?DW
SOP 鈥?NS
SSOP 鈥?DB
TSSOP 鈥?PW
TVSOP 鈥?DGV
CDIP 鈥?J
鈥?5擄C to 125擄C
CFP 鈥?W
LCCC 鈥?FK
PACKAGE鈥?/div>
Tube
Tube
Tape and reel
鈥?0擄C to 85擄C
Tape and reel
Tape and reel
Tube
Tape and reel
Tape and reel
Tube
Tube
Tube
ORDERABLE
PART NUMBER
SN74AHC574N
SN74AHC574DW
SN74AHC574DWR
SN74AHC574NSR
SN74AHC574DBR
SN74AHC574PW
SN74AHC574PWR
SN74AHC574DGVR
SNJ54AHC574J
SNJ54AHC574W
SNJ54AHC574FK
AHC574
HA574
HA574
HA574
SNJ54AHC574J
SNJ54AHC574W
SNJ54AHC574FK
TOP-SIDE
MARKING
SN74AHC574N
AHC574
鈥?Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Copyright
錚?/div>
2003, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
8D
GND
CLK
8Q
7Q
1

5962-9685401QSA 產(chǎn)品屬性

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