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5962-9584301Q2A Datasheet

  • 5962-9584301Q2A

  • OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS

  • 14頁

  • TI

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SN54ABT533, SN74ABT533
OCTAL TRANSPARENT D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS186A 鈥?FEBRUARY 1991 鈥?REVISED JULY 1994
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
State-of-the-Art
EPIC-
螜螜
B
鈩?/div>
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA
Per JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce)
< 1 V at V
CC
= 5 V, T
A
= 25擄C
High-Drive Outputs (鈥?32-mA I
OH
,
64-mA I
OL
)
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic
Chip Carriers (FK), and Plastic (N) and
Ceramic (J) DIPs
SN54ABT533 . . . J PACKAGE
SN74ABT533 . . . DB, DW, OR N PACKAGE
(TOP VIEW)
OE
1Q
1D
2D
2Q
3Q
3D
4D
4Q
GND
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
V
CC
8Q
8D
7D
7Q
6Q
6D
5D
5Q
LE
description
The
鈥睞BT533
are 8-bit transparent D-type latches
with 3-state outputs designed specifically for
driving highly capacitive or relatively low-
impedance loads. They are particularly suitable
for implementing buffer registers, I/O ports,
bidirectional bus drivers, and working registers.
When the latch-enable (LE) input is high, the
Q outputs follow the complements of the data
(D) inputs. When LE is taken low, the Q outputs
are latched at the inverse of the levels set up at the
D inputs. The
鈥睞BT533
provides inverted data at
its outputs.
SN54ABT533 . . . FK PACKAGE
(TOP VIEW)
1D
1Q
OE
V
CC
2D
2Q
3Q
3D
4D
4
5
6
7
8
3 2 1 20 19
18
17
16
15
14
9 10 11 12 13
8Q
8D
7D
7Q
6Q
6D
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low logic levels) or a high-impedance state. In the high-impedance state, the outputs neither load nor drive
the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus
lines without need for interface or pullup components.
OE does not affect the internal operations of the latches. Previously stored data can be retained or new data
can be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74ABT533 is available in TI鈥檚 shrink small-outline package (DB), which provides the same I/O pin count
and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54ABT533 is characterized for operation over the full military temperature range of 鈥?55擄C to 125擄C. The
SN74ABT533 is characterized for operation from 鈥?40擄C to 85擄C.
EPIC-螜螜B is a trademark of Texas Instruments Incorporated.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303
Copyright
漏
1994, Texas Instruments Incorporated
鈥?/div>
DALLAS, TEXAS 75265
4Q
GND
LE
5Q
5D
2鈥?

5962-9584301Q2A 產(chǎn)品屬性

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