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5962-9571201QKA Datasheet

  • 5962-9571201QKA

  • 9-BIT BUS-INTERFACE D-TYPE LATCHES WITH 3-STATE OUTPUTS

  • 17頁

  • TI

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SN54ABT843, SN74ABT843
9-BIT BUS-INTERFACE D-TYPE LATCHES
WITH 3-STATE OUTPUTS
SCBS197D 鈥?FEBRUARY 1991 鈥?REVISED MAY 1997
D
D
D
D
D
State-of-the-Art
EPIC-
螜螜
B
鈩?/div>
BiCMOS Design
Significantly Reduces Power Dissipation
Latch-Up Performance Exceeds 500 mA Per
JEDEC Standard JESD-17
Typical V
OLP
(Output Ground Bounce) < 1 V
at V
CC
= 5 V, T
A
= 25擄C
High-Drive Outputs (鈥?2-mA I
OH
, 64-mA I
OL
)
Package Options Include Plastic
Small-Outline (DW) and Shrink
Small-Outline (DB) Packages, Ceramic Chip
Carriers (FK), Ceramic Flat (W) Package,
and Plastic (NT) and Ceramic (JT) DIPs
SN54ABT843 . . . JT OR W PACKAGE
SN74ABT843 . . . DB, DW, OR NT PACKAGE
(TOP VIEW)
description
The 鈥橝BT843 9-bit latches are designed
specifically for driving highly capacitive or
relatively low-impedance loads. They are
particularly suitable for implementing buffer
registers, I/O ports, bidirectional bus drivers, and
working registers.
The nine transparent D-type latches provide true
data at the outputs.
A buffered output-enable (OE) input can be used
to place the nine outputs in either a normal logic
state (high or low logic levels) or a
high-impedance state. The outputs are also in the
high-impedance state during power-up and
power-down conditions. The outputs remain in the
high-impedance state while the device is powered
down. In the high-impedance state, the outputs
neither load nor drive the bus lines significantly.
The high-impedance state and increased drive
provide the capability to drive bus lines without
need for interface or pullup components.
3D
4D
5D
NC
6D
7D
8D
OE
1D
2D
3D
4D
5D
6D
7D
8D
9D
CLR
GND
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
1Q
2Q
3Q
4Q
5Q
6Q
7Q
8Q
9Q
PRE
LE
SN54ABT843 . . . FK PACKAGE
(TOP VIEW)
4
5
6
7
8
9
10
3 2 1 28 27 26
25
24
23
22
21
20
OE
NC
V
CC
1Q
2Q
3Q
4Q
5Q
NC
6Q
7Q
8Q
11
19
12 13 14 15 16 17 18
NC 鈥?No internal connection
OE does not affect the internal operations of the latch. Previously stored data can be retained or new data can
be entered while the outputs are in the high-impedance state.
To ensure the high-impedance state during power up or power down, OE should be tied to V
CC
through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN54ABT843 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C. The
SN74ABT843 is characterized for operation from 鈥?0擄C to 85擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC-螜螜B is a trademark of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
9D
CLR
GND
NC
LE
PRE
9Q
Copyright
漏
1997, Texas Instruments Incorporated
2D
1D
1

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