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5962-9466902QXA Datasheet

  • 5962-9466902QXA

  • DIGITAL SIGNAL PROCESSORS

  • 62頁(yè)

  • TI

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SMJ320C40, TMP320C40
DIGITAL SIGNAL PROCESSORS
SGUS017H 鈥?OCTOBER 1993 鈥?REVISED OCTOBER 2001
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SMJ: QML Processing to MIL鈥揚(yáng)RF鈥?8535
SM: Standard Processing
TMP: Commercial Level Processing TAB
Operating Temperature Ranges:
鈥?Military (M) 鈥?5擄C to 125擄C
鈥?Special (S) 鈥?5擄C to 100擄C
鈥?Commercial (C) 鈥?5擄C to 85擄C
鈥?Commercial (L) 0擄C to 70擄C
Highest Performance Floating-Point Digital
Signal Processor (DSP)
鈥?C40-60:
33-ns Instruction Cycle Time:
60 MFLOPS, 30 MIPS, 330 MOPS,
384 MBps
鈥?C40-50:
40-ns Instruction Cycle Time:
50 MFLOPS, 25 MIPS, 275 MOPS,
320 MBps
鈥?C40-40:
50-ns Instruction Cycle Time:
40 MFLOPS, 20 MIPS, 220 MOPS,
256 MBps
Six Communications Ports
6-Channel Direct Memory Access (DMA)
Coprocessor
Single-Cycle Conversion to and From
IEEE-745 Floating-Point Format
Single Cycle 1/x, 1/ x
Source-Code Compatible With SMJ320C30
Validated Ada Compiler
Single-Cycle 40-Bit Floating-Point,
32-Bit Integer Multipliers
12 40-Bit Registers, 8 Auxiliary Registers,
14 Control Registers, and 2 Timers
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IEEE Standard 1149.1
鈥?/div>
Test-Access Port
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(JTAG)
Two Identical External Data and Address
Buses Supporting Shared Memory Systems
and High Data-Rate, Single-Cycle
Transfers:
鈥?High Port-Data Rate of 100 MBytes/s
(Each Bus)
鈥?16G-Byte Continuous
Program/Data/Peripheral Address Space
鈥?Memory-Access Request for Fast,
Intelligent Bus Arbitration
鈥?Separate Address-, Data-, and
Control-Enable Pins
鈥?Four Sets of Memory-Control Signals
Support Different Speed Memories in
Hardware
Packaging:
鈥?325-Pin Ceramic Grid Array (GF Suffix)
鈥?352-Lead Ceramic Quad Flatpack
(HFH Suffix)
鈥?324-Pad JEDEC-Standard TAB Frame
Fabricated Using Enhanced Performance
Implanted CMOS (EPIC錚? Technology by
Texas Instruments (TI錚?
Separate Internal Program, Data, and DMA
Coprocessor Buses for Support of Massive
Concurrent Input/Output (I/O) of Program
and Data Throughput, Maximizing
Sustained Central Processing Unit (CPU)
Performance
On-Chip Program Cache and
Dual-Access/Single-Cycle RAM for
Increased Memory-Access Performance
鈥?512-Byte Instruction Cache
鈥?8K Bytes of Single-Cycle Dual-Access
Program or Data RAM
鈥?ROM-Based Bootloader Supports
Program Bootup Using 8-, 16-, or 32-Bit
Memories Over Any One of the
Communications Ports
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
鈥營(yíng)EEE Standard 1149.1-1990, IEEE Standard Test-Access Port and Boundary-Scan Architecture.
EPIC and TI are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
錚?/div>
2001, Texas Instruments Incorporated
On products compliant to MIL PRF 38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 1443
鈥?/div>
HOUSTON, TEXAS 77251鈥?443
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5962-9466902QXA 產(chǎn)品屬性

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