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5962-9323901Q3A Datasheet

  • 5962-9323901Q3A

  • SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES SCAN-CONTR...

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  • TI

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SN54ACT8997, SN74ACT8997
SCAN-PATH LINKERS WITH 4-BIT IDENTIFICATION BUSES
SCAN-CONTROLLED IEEE STD 1149.1 (JTAG) TAP CONCATENATORS
SCAS157D 鈥?APRIL 1990 鈥?REVISED DECEMBER 1996
D
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Members of the Texas Instruments
SCOPE
鈩?/div>
Family of Testability Products
Compatible With the IEEE Standard
1149.1-1990 (JTAG) Serial Test Bus
Allow Partitioning of System Scan Paths
Can Be Cascaded Horizontally or Vertically
Select Up to Four Secondary Scan Paths to
Be Included in a Primary Scan Path
Include 8-Bit Programmable Binary Counter
to Count or Initiate Interrupt Signals
Include 4-Bit Identification Bus for
Scan-Path Identification
Inputs Are TTL Compatible
EPIC
鈩?/div>
(Enhanced-Performance Implanted
CMOS) 1-碌m Process
Package Options Include Plastic
Small-Outline (DW) Packages, Ceramic
Chip Carriers (FK), and Standard Plastic
(NT) and Ceramic (JT) 300-mil DIPs
SN54ACT8997 . . . JT PACKAGE
SN74ACT8997 . . . DW OR NT PACKAGE
(TOP VIEW)
DCO
MCO
DTDO1
DTDO2
DTDO3
DTDO4
GND
DTMS1
DTMS2
DTMS3
DTMS4
DTCK
TDO
TMS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
DCI
MCI
TRST
ID1
ID2
ID3
ID4
V
CC
DTDI1
DTDI2
DTDI3
DTDI4
TDI
TCK
SN54ACT8997 . . . FK PACKAGE
(TOP VIEW)
description
The 鈥橝CT8997 are members of the Texas
Instruments SCOPE鈩?testability integrated-
circuit family. This family of components facilitates
testing of complex circuit-board assemblies.
The 鈥橝CT8997 enhance the scan capability of TI鈥檚
SCOPE鈩?family by allowing augmentation of a
system鈥檚 primary scan path with secondary scan
paths (SSPs), which can be individually selected
by the 鈥橝CT8997 for inclusion in the primary scan
path. These devices also provide buffering of test
signals to reduce the need for external logic.
TRST
MCI
DCI
DCO
MCO
DTDO1
DTDO2
5
6
7
8
9
ID1
ID2
ID3
ID4
V
CC
DTDI1
DTDI2
4 3
2 1 28 27 26
25
24
23
22
21
20
10
11
19
12 13 14 15 16 17 18
DTDI3
DTDI4
TDI
TCK
TMS
TDO
DTCK
By loading the proper values into the instruction
register and data registers, the user can select up
to four SSPs to be included in a primary scan path. Any combination of the SSPs can be selected at a time. Any
of the device鈥檚 six data registers or the instruction register can be placed in the device鈥檚 scan path, i.e., placed
between test data input (TDI) and test data output (TDO) for subsequent shift and scan operations.
All operations of the device except counting are synchronous to the test clock pin (TCK). The 8-bit
programmable up/down counter can be used to count transitions on the device condition input (DCI) pin and
output interrupt signals via the device condition output (DCO) pin. The device can be configured to count on
either the rising or falling edge of DCI.
The test access port (TAP) controller is a finite-state machine compatible with IEEE Standard 1149.1.
The SN54ACT8997 is characterized for operation over the full military temperature range of 鈥?5擄C to 125擄C.
The SN74ACT8997 is characterized for operation from 0擄C to 70擄C.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
DTDO3
DTDO4
GND
DTMS1
DTMS2
DTMS3
DTMS4
Copyright
漏
1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
1

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