The 鈥橝CT8990 test-bus controllers (TBC) are members of the Texas Instruments SCOPE鈩?testability
integrated-circuit family. This family of components supports IEEE Standard 1149.1-1990 (JTAG) boundary
scan to facilitate testing of complex circuit-board assemblies. The 鈥橝CT8990 differ from other SCOPE鈩?/div>
integrated circuits. Their function is to control the JTAG serial-test bus rather than being target
boundary -scannable devices.
The required signals of the JTAG serial-test bus 鈥?test clock (TCK), test mode select (TMS), test data input (TDI),
and test data output (TDO) can be connected from the TBC to a target device without additional logic. This is
done as a chain of IEEE Standard 1149.1-1990 boundary-scannable components that share the same
serial-test bus. The TBC generates TMS and TDI signals for its target(s), receives TDO signals from its target(s),
and buffers its test clock input (TCKI) to a test clock output (TCKO) for distribution to its target(s). The TMS, TDI,
and TDO signals can be connected to a target directly or via a pipeline, with a retiming delay of up to 31 bits.
Since the TBC can be configured to generate up to six separate TMS signals [TMS (5 鈥?0)], it can be used to
control up to six target scan paths that are connected in parallel (i.e., sharing common TCK, TDI, and TDO
signals).
While most operations of the TBC are synchronous to TCKI, a test-off (TOFF) input is provided for output control
of the target interface, and a test-reset (TRST) input is provided for hardware/software reset of the TBC. In
addition, four event [EVENT (3 鈥?0)] I/Os are provided for asynchronous communication to target device(s).
Each event has its own event generation/detection logic, and detected events can be counted by two 16-bit
counters.
The TBC operates under the control of a host microprocessor/microcontroller via the 5-bit address bus
[ADRS (4 鈥?0)] and the 16-bit read/write data bus [DATA (15 鈥?0)]. Read (RD) and write (WR) strobes are
implemented such that the critical host-interface timing is independent of the TCKI period. Any one of
24 registers can be addressed for read and/or write operations. In addition to control and status registers, the
TBC contains two command registers, a read buffer, and a write buffer. Status of the TBC is transmitted to the
host via ready (RDY) and interrupt (INT) outputs.
Major commands can be issued by the host to cause the TBC to generate the TMS sequences necessary to
move the target(s) from any stable test-access-port (TAP) controller state to any other stable TAP state, to
execute instructions in the Run-Test/Idle TAP state, or to scan instruction or test data through the target(s). A
32-bit counter can be preset to allow a predetermined number of execution or scan operations.
Serial data that appears at the selected TDI input (TDI1 or TDI0) is transferred into the read buffer, which can
be read by the host to obtain up to 16 bits of the serial-data stream. Serial data that is transmitted from the TDO
output is written by the host to the write buffer.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE and EPIC are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright
漏
1997, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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