Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modi鏗乪d to remove devices not offered.
CY29FCT520T
SCCS011A - May 1994 - Revised April 2000
Multi-Level Pipeline Register
Functional Description
The CY29FCT520T devices are multilevel 8-bit-wide pipeline
registers. The devices consist of four registers, A1, A2, B1,
and B2, which are con鏗乬ured by the instruction inputs I
0
, I
1
as
a single 4-level pipeline or as two two-level pipelines. The
contents of any register may be read at the multiplexed out-
put at any time by using the mux-selection controls S
0
and
S
1
.
The pipeline registers are positive edge triggered and data is
shifted by the rising edge of the clock input. Instruction I=0
selects the four-level pipeline mode. Instruction I=1 selects the
two-level B pipeline while I=2 selects the two-level A pipeline.
I=3 is the HOLD instruction; no shifting is performed by the
clock in this mode.
In the two-level operation mode, data is shifted from level 1 to
level 2 and new data is loaded into level 1.
The outputs are designed with a power-off disable feature to
allow for live insertion of boards.
Features
鈥?/div>
Function, pinout, and drive compatible with FCT, F
Logic, and AM29520
鈥?/div>
FCT-C speed at 6.0 ns max. (Com鈥檒),
FCT-B speed at 7.5 ns max. (Com鈥檒),
FCT-A speed at 14.0 ns max. (Com鈥檒)
鈥?/div>
Reduced V
OH
(typically = 3.3V) versions of equivalent
FCT functions
鈥?/div>
Edge-rate control circuitry for signi鏗乧antly improved
noise characteristics
鈥?/div>
Power-Off disable feature
鈥?/div>
Matched rise and fall times
鈥?/div>
Fully compatible with TTL input and output logic levels
鈥?/div>
ESD > 2000V
鈥?Sink current
64 mA (Com鈥檒), 32 mA (Mil)
Source current
32 mA (Com鈥檒), 12 mA (Mil)
鈥?/div>
Single and dual pipeline operation modes
鈥?/div>
Multiplexed data inputs and outputs
Logic Block Diagram
8
D
0
鈥揇
7
Pin Configurations
DIP, SOIC, QSOP, CDIP
Top View
INSTRUCTION
I
0
I
1
CLOCK
REGISTER
CONTROLS
MUX
I
0
I
1
D
0
D
1
D
2
D
3
D
4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
19
18
17
16
15
14
13
V
CC
S
0
S
1
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
OE
OCTAL REG
A1
OCTAL REG
B1
MUX S
0
SEL S
1
OCTAL REG
A2
OCTAL REG
B2
D
5
D
6
D
7
CLK
GND
MUX
OE
8
Y
0
鈥揧
7
Pipeline Instruction Table
I=0
I
1
= 0
I
0
= 0
I=1
I
1
= 0
I
0
= 1
I=2
I
1
= 1
I
0
= 0
I
1
= 1
I=3
I
0
= 1
A1
B1
A1
B1
A1
B1
A1
B1
A2
B2
A2
B2
A2
B2
A2
B2
Single four-level
Dual two-level
Hold
Copyright
漏
2000, Texas Instruments Incorporated
5962-9220504MLA 產(chǎn)品屬性
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