CD74HC390,
CD54HCT390, CD74HCT390
Data sheet acquired from Harris Semiconductor
SCHS185C
September 1997 - Revised October 2003
High-Speed CMOS Logic
Dual Decade Ripple Counter
Description
The CD74HC390 and 鈥橦CT390 dual 4-bit decade ripple
counters are high-speed silicon-gate CMOS devices and are
pin compatible with low-power Schottky TTL (LSTTL). These
devices are divided into four separately clocked sections.
The counters have two divide-by-2 sections and two divide-
by-5 sections. These sections are normally used in a BCD
decade or bi-quinary con鏗乬uration, since they share a com-
mon master reset (nMR). If the two master reset inputs (1MR
and 2MR) are used to simultaneously clear all 8 bits of the
counter, a number of counting con鏗乬urations are possible
within one package. The separate clock inputs (nCP0 and
nCP1) of each section allow ripple counter or frequency divi-
sion applications of divide-by-2, 4. 5, 10, 20, 25, 50 or 100.
Each section is triggered by the High-to-Low transition of the
input pulses (nCP0 and nCP1).
For BCD decade operation, the nQ0 output is connected to
the nCP1 input of the divide-by-5 section. For bi-quinary
decade operation, the nO3 output is connected to the nCP0
input and nQ
0
becomes the decade output.
The master reset inputs (1MR and 2MR) are active-High
asynchronous inputs to each decade counter which oper-
ates on the portion of the counter identi鏗乪d by the 鈥?鈥?and 鈥?鈥?/div>
pre鏗亁es in the pin con鏗乬uration. A High level on the nMR
input overrides the clock and sets the four outputs Low.
Features
鈥?Two BCD Decade or Bi-Quinary Counters
[ /Title
(CD74
HC390
,
CD74
HCT39
0)
/Sub-
ject
(High
Speed
CMOS
鈥?One Package Can Be Con鏗乬ured to Divide-by-2, 4,
5,10, 20, 25, 50 or 100
鈥?Two Master Reset Inputs to Clear Each Decade
Counter Individually
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
Ordering Information
PART NUMBER
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Pinout
CD54HCT390
(CERDIP)
CD74HC390, CD74HCT390
(PDIP, SOIC)
TOP VIEW
1CP0 1
1MR 2
1Q
0
3
1CP1 4
1Q
1
5
1Q
2
6
1Q
3
7
GND 8
16 V
CC
15 2CP0
14 2MR
13 2Q0
12 2CP1
11 2Q
1
10 2Q
2
9 2Q
3
CD54HCT390F3A
CD74HC390E
CD74HC390M
CD74HC390MT
CD74HC390M96
CD74HCT390E
CD74HCT390M
CD74HCT390MT
CD74HCT390M96
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel
of 250.
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
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