CD54HC10, CD74HC10,
CD54HCT10, CD74HCT10
Data sheet acquired from Harris Semiconductor
SCHS128C
August 1997 - Revised September 2003
High-Speed CMOS Logic
Triple 3-Input NAND Gate
Description
The 鈥橦C10 and 鈥橦CT10 logic gates utilize silicon gate CMOS
technology to achieve operating speeds similar to LSTTL
gates with the low power consumption of standard CMOS
integrated circuits. All devices have the ability to drive 10
LSTTL loads. The HCT logic family is functionally pin
compatible with the standard LS logic family.
[ /Title
(CD74
HC10,
CD74
HCT10
)
/Sub-
ject
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate)
/Autho
r ()
/Key-
words
(High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
High
Speed
CMOS
Logic
Triple
3-Input
NAND
Gate,
Harris
Semi-
Features
鈥?Buffered Inputs
鈥?Typical Propagation Delay: 8ns at V
CC
= 5V,
C
L
= 15pF, T
A
= 25
o
C
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC10F3A
CD54HCT10F3A
CD74HC10E
CD74HC10M
CD74HC10MT
CD74HC10M96
CD74HCT10E
CD74HCT10M
CD74HCT10MT
CD74HCT10M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
14 Ld CERDIP
14 Ld CERDIP
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
14 Ld PDIP
14 Ld SOIC
14 Ld SOIC
14 Ld SOIC
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel
of 250.
Pinout
CD54HC10, CD54HCT10
(CERDIP)
CD74HC10, CD74HCT10
(PDIP, SOIC)
TOP VIEW
1A 1
1B 2
2A 3
2B 4
2C 5
2Y 6
GND 7
14 V
CC
13 1C
12 1Y
11 3C
10 3B
9 3A
8 3Y
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
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