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5962-8974301EA Datasheet

  • 5962-8974301EA

  • High-Speed CMOS Logic Hex D-Type Flip-Flop with Reset

  • 12頁(yè)

  • TI

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CD54HC174, CD74HC174,
CD54HCT174, CD74HCT174
Data sheet acquired from Harris Semiconductor
SCHS159C
August 1997 - Revised October 2003
High-Speed CMOS Logic
Hex D-Type Flip-Flop with Reset
times is transferred to the Q output on the low to high
transition of the CLOCK input. The MR input, when low, sets
all outputs to a low state.
Each output can drive ten low power Schottky TTL
equivalent loads. The 鈥橦CT174 is functional as well as, pin
compatible to the 鈥橪S174.
Features
鈥?Buffered Positive Edge Triggered Clock
[ /Title
(CD74
HC174
,
CD74
HCT17
4)
/Sub-
ject
(High
Speed
CMOS
Logic
Hex D-
Type
Flip-
Flop
鈥?Asynchronous Common Reset
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A(chǔ) at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC174F3A
CD54HCT174F3A
CD74HC174E
CD74HC174M
CD74HC174MT
CD74HC174M96
CD74HCT174E
CD74HCT174M
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Description
The 鈥橦C174 and 鈥橦CT174 are edge triggered flip-flops which
utilize silicon gate CMOS circuitry to implement D-type flip-
flops. They possess low power and speeds comparable to low
power Schottky TTL circuits. The devices contain six master-
slave 鏗俰p-鏗俹ps with a common clock and common reset.
Data on the D input having the speci鏗乪d setup and hold
CD74HCT174MT
CD74HCT174M96
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel of
250.
Pinout
CD54HC174, CD54HCT174
(CERDIP)
CD74HC174, CD74HCT174
(PDIP, SOIC)
TOP VIEW
MR 1
Q
0
2
D
0
3
D
1
4
Q
1
5
D
2
6
Q
2
7
GND 8
16 V
CC
15 Q
5
14 D
5
13 D
4
12 Q
4
11 D
3
10 Q
3
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

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