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5962-8970101EA Datasheet

  • 5962-8970101EA

  • High-Speed CMOS Logic Quad D-Type Flip-Flop with Reset

  • 12頁

  • TI

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CD54HC175, CD74HC175,
CD54HCT175, CD74HCT175
Data sheet acquired from Harris Semiconductor
SCHS160C
August 1997 - Revised October 2003
High-Speed CMOS Logic
Quad D-Type Flip-Flop with Reset
advantage of standard CMOS ICs and the ability to drive 10
LSTTL devices.
Information at the D input is transferred to the Q, Q outputs on
the positive going edge of the clock pulse. All four Flip-Flops
are controlled by a common clock (CP) and a common reset
(MR). Resetting is accomplished by a low voltage level
independent of the clock. All four Q outputs are reset to a
logic 0 and all four Q outputs to a logic 1.
Features
[ /Title
(CD74
HC175
,
CD74
HCT17
5)
/Sub-
ject
(High
Speed
CMOS
Logic
Quad
D-
Type
Flip-
鈥?Common Clock and Asynchronous Reset on Four
D-Type Flip-Flops
鈥?Positive Edge Pulse Triggering
鈥?Complementary Outputs
鈥?Buffered Inputs
鈥?Fanout (Over Temperature Range)
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
鈥?Wide Operating Temperature Range . . . -55
o
C to 125
o
C
鈥?Balanced Propagation Delay and Transition Times
鈥?Signi鏗乧ant Power Reduction Compared to LSTTL
Logic ICs
鈥?HC Types
- 2V to 6V Operation
- High Noise Immunity: N
IL
= 30%, N
IH
= 30% of V
CC
at V
CC
= 5V
鈥?HCT Types
- 4.5V to 5.5V Operation
- Direct LSTTL Input Logic Compatibility,
V
IL
= 0.8V (Max), V
IH
= 2V (Min)
- CMOS Input Compatibility, I
l
鈮?/div>
1碌A at V
OL
, V
OH
Ordering Information
PART NUMBER
CD54HC175F3A
CD54HCT175F3A
CD74HC175E
CD74HC175M
CD74HC175MT
CD74HC175M96
CD74HCT175E
CD74HCT175M
CD74HCT175MT
CD74HCT175M96
TEMP. RANGE
(
o
C)
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
-55 to 125
PACKAGE
16 Ld CERDIP
16 Ld CERDIP
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
16 Ld PDIP
16 Ld SOIC
16 Ld SOIC
16 Ld SOIC
Description
The 鈥橦C175 and 鈥橦CT175 are high speed Quad D-type Flip-
Flops with individual D-inputs and Q, Q complementary
outputs. The devices are fabricated using silicon gate CMOS
technology. They have the low power consumption
NOTE: When ordering, use the entire part number. The suf鏗亁 96
denotes tape and reel. The suf鏗亁 T denotes a small-quantity reel of
250.
Pinout
CD54HC175, CD54HCT175
(CERDIP)
CD74HC175, CD74HCT175
(PDIP, SOIC)
TOP VIEW
MR 1
Q
0
2
Q
0
3
D
0
4
D
1
5
Q
1
6
Q
1
7
GND 8
16 V
CC
15 Q
3
14 Q
3
13 D
3
12 D
2
11 Q
2
10 Q
2
9 CP
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright
漏
2003, Texas Instruments Incorporated
1

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